Trade-Offs in Cognitive Radio Architectures
C. Patrick YueDept. of ECE, CMU
Cognitive radio is the essential technology for enabling dynamic usage of frequency spectrum to increase spectral efficiency in future wireless standards. Cognitive radios are implemented by combining software radios with cognition capabilities. Software radio is an emerging technology of flexible radio systems that can be reconfigured and reprogrammed through software to support multi-band and multi-mode operation. Based on cognition of wireless channel characteristics, network loading, and user service requirements, the software radio settings are defined. To attain cognition, novel sensors must be integrated in the radio with high-performance signal processing to model the environment. The key enabling technologies for realizing cognitive radios are:
· High-performance analog-to-digital converters (ADC) for digitizing the signal as close to the antenna as possible to allow digital signal processing early in the signal path.
· Cognition sensors and models for the radio attributes such as RF bands, air interface, user needs, etc.
· Low-power, high-performance DSP processors to replace application-specific integrated circuits (ASIC) for bandband (BB) signal processing.
· Multi-band RF front-end circuits including band-select filters, low-noise amplifiers, power amplifiers and transmit/receive switches.
This paper reviews the trade-offs of the plausible radio architectures for cognitive radios. In particular, direct RF digitization, digital intermediate-frequency (IF) and direct conversion architecture will be examined.
Conventional radio architectures can be categorized as heterodyne and homodyne systems. In heterodyne radios, the BB signals are translated to, or from, the RF in two steps. The intermediate-frequency (IF) is introduced to relax the requirement on the channel select filters. Homodyne systems, also known as direct conversion or zero-IF architecture, convert the signal between BB and RF in a single step. For cognitive radios, the design goal is to minimize custom hardware and to maximize programmable DSP usage by digitizing the signal early in the transceiver chain. The radio architecture is therefore dictated by the attainable ADC performance since it determines whether the analog-to-digital conversion can be executed at RF, IF, or BB. The main performance specifications of an ADC are sampling speed, resolution, linearity and power consumption. Direct digitization of the RF signal requires Nyquist sampling speed between 2 to 5GS/s for most existing and emerging cellular applications such as GSM and W-CDMA. The wide dynamic range of the RF input signal mandate a resolution at the level of 10 to 15bit. For instance, GSM incoming signals can range from –100dBm to –10dBm resulting in a dynamic range of 90dB, which corresponds to 15-bit resolution. State of the art ADC can achieve 6-bit resolution at 4GS/s dissipating almost 1W in 0.13µm standard CMOS technology based on a flash architecture [1]. In order to increase the sampling speed and resolution, it will required a drastic increase in power consumption. For example, 8-bit resolution at 20GS/s has been achieved while consuming 10W [2]. In the foreseeable future, it will be impossible to implement ADCs operating at 5GS/s and a resolution of 15-bit while meeting the low-power budget for mobile devices. This makes directly sampling the RF signal impractical.
The second option is to digitize the signal at IF, which can range from 50MHz to several hundred MHz. In a digital-IF transceiver as shown in Figure 1, the conversion from RF to IF will be performed in the analog domain. By using a fixed ADC sampling rate enables the use of fixed-width RF and anti-alias analog filters and the generation of a unique RF oscillator frequency. After the IF signal is digitized, a programmable IF DSP processor performs the downconversion to BB, channel selection, and sample rate conversion. The choice of IF is determined by the trade-off between the requirement for the RF image reject filter and the IF channel select filter. The ADC design is relaxed with a low IF since the sampling speed is reduced. However, lowering the IF means that the RF image reject filter need to provide a steeper attenuation slope as the image frequency is closer to the RF signal. The high-Q requirement of the image reject filter implies the need of off-chip SAW filters, which is undesirable for high-level integration. To avoid this problem, image reject mixers driven by quadrature LO can be used can be employed. However, on-chip component mismatch must be minimized to achieve good matching between I and Q signal paths.
Direct conversion architecture is a promising solution for cognitive radio. As shown in Figure 2, the RF signals are downconverted to baseband by a pair of quadrature mixers. The IQ signals are then filtered with anti-alias filters followed by automatic gain control before feeding into the ADCs. Channel selection is performed in the digital domain at baseband. In direct conversion, image signal is absent and hence the need for image reject filter is eliminated, which greatly simplifies the transceiver design. However, since the signal is directly convert to DC, any DC offset at the output of the mixer will corrupt the signal content near DC. The origins of DC offset include LO leakage and self mixing, mismatch in switching devices in mixer, non-50% LO drive, and even-order non-linearity in the mixer. DC offset calibration scheme must be implemented to ensure proper operation.
Reference
[1] C. Paulus et al., “A 4 GS/s 6b Flash ADC in 0.13µm CMOS”, 2004 VLSI Circuit Symposium.
[2] K. Poulton et al., “A 20GS/s 8b ADC with a 1MB Memory in 0.18um CMOS,” ISSCC 2003, pp. 318-319.
Figure 1. Digital-IF receiver architecture.
Figure 2. Direct conversion receiver architecture.
C. Patrick Yue Page 3of 3 7/26/2004