5

EECS 141: SPRING 08 — CLASS PROJECT REPORT: PHASE 1 NAME STUDENT A, NAME STUDENT B

University of California

College of Engineering

Department of Electrical Engineering

and Computer Sciences

J. Rabaey WeFr 2-3:30pm

Wednesday, April 6th

5

EECS 141: SPRING 08 — CLASS PROJECT REPORT: PHASE 1 NAME STUDENT A, NAME STUDENT B

EECS 141: CLASS PROJECT — PHASE 1 REPORT

STUDENT A:

NAME / Last First
SID

STUDENT B:

NAME / Last First
SID

a)  Timing Characteristic of Full Adder and Register Cells

Provide each of the timing characteristic in the form of

Full Adder:

tpaàs =

tpbàs =

tpcinàs =

tpaàcout =

tpbàcout =

tpcinàcout =

Register Cell:

tpclkàq =

b)  Filter Block Diagram and Functionality:

1.  Provide a diagram of the top level schematic of your filter containing the 8-bit registers and adders, as well as a schematic of your 8-bit adder.

Filter Block Diagram (Schematic):

8-bit Adder Schematic:

2.  Provide a plot of the simulation of the impulse response. Use unsigned magnitude as representation of you input signal. Make sure you show clearly what your input signal is and how your output signal looks like. Set up a simulation similar to the one shown in the document on the testbench setup (posted on the webpage as well). You don’t have to use the ADC and DAC at the input and the output but you might find it useful. If you decide to use it, use the dac-8bit-ideal building block from the ahdlLib to simplify interpretation of the output signal. When doing so make sure you specify all the parameters of the DAC (e.g. vref, vtrans, etc.) so that they make sense. Also use the 8-bit-ideal building block from the same library to create the input stimuli (make sure you set the parameters here as well).

Comment on the results and explain why they verify that your design is correct.

Simulation Results for Impulse Response

3.  What is the maximum input impulse that can be applied to the filter without causing any overflow in any of the internal adders? What is the maximum amplitude that can be applied when the input is a step function?

c)  Critical Path: Analytical

1.  Show the critical path (highlight it in your top level schematic in you design) and explain why the one you found is actually the critical one.

Top Level Schematic of Filter with Highlighted Critical Path:

2.  Give an input pattern that excites the critical path in your design.

3.  Using the results from a), estimate the delay of your critical path (show the expression don’t provide purely the numerical solution)

tp,critical path =

d)  Critical Path: Simulation

1.  Simulate the delay of your critical path using SPECTRE and provide the result

tp,critical path, sim =

2.  Reasons for mismatch between the simulated and estimated delay are:

e)  Power Estimation:

Estimate and simulate the dynamic power dissipation of your filter when applying the following input sequence:

177, 149, 68, 204, 7

Each input signal is applied for one clock cycle. Make sure all your register outputs are set to 0 at the beginning of the simulation by either starting by applying 0 to the input for several clock cycles or use initial conditions to set all internal nodes to 0. Average the power dissipation over the 5 clock signals the input sequence is actually applied (Hint: Use the calculator to determine the average values of the entities you are interested in. You might also find the “clip” comment useful which allows you to cut out a time slice of a signal.) Clock your circuit at 100MHz but neglect the power dissipated by the clock signal.

1.  Analytically derive the power dissipation for the given input sequence. Explain your derivation and provide the final result.

Pfilter =

2.  Simulate the actually power dissipation and compare it to your estimate

Pfilter,sim =

5

EECS 141: SPRING 08 — CLASS PROJECT REPORT: PHASE 1 NAME STUDENT A, NAME STUDENT B