CSUS, COLLEGE OF ENGINEERING AND COMPUTER SCIENCE
Program in Computer Engineering, Department of Computer Science
CPE 185 - Computer Interfacing, Spring 2006 (TR 9-1015 LIB 127)
INSTRUCTOR:I. Ghansah
Office: RVR-4004Phone:278-7659Email:
WWW:
Office Hours: M 4:30-5:45p, T 10:15a-12p; or by appointment.
Laboratory Instructor: Ghansah
CATALOG DESCRIPTION:
Design of 16 and 32 bit microcomputer systems including memory systems, parallel and serial input/output, timer modules and interrupt structures; designing “C” language code, in laboratory, to exercise interface modules of parallel and serial input/output, timer modules and interrupts; extensive study of interrupt handlers, assemblers, linkers, and loaders. Practical features of interfaces; handshaking techniques, displays, keypads, trackball, are included.
Prerequisites: Knowledge of logic design and basic computer architecture (CpE 64) and intro to machine organization and program design principles (CSc 35); Unix and C (CSc 60) Desirable. 4 Units
Prerequisite Proof:
The department now has a policy requiring every student in every course to provide transcripts showing proof that they have appropriate prerequisites. Every student must provide this documentation in order to be permitted to enroll in this course. It is the responsibility of the student to provide such documentation by providing a transcript with the said prerequisites highlighted.To do this you must submit to the instructor a copy of the CasperWeb Academic Information report entitled “Transfer and CSUS Credit Summary”. This must be done within the first two weeks of classes. Any student who does not provide such verification will be dropped from the class. Any student who has completed one or more prerequisites at another school must provide similar verification to the instructor. NOTE: be sure to provide the report specifically titled “Transfer and CSUS Credit Summary”. Other CasperWeb forms (such as the “Academic Record” form) will not be accepted.
Repeat Policy:
The department has a policy specifying that students may not repeat a Computer Science course more than once. Any student who wishes to repeat a course more than once (that is, take a course for a third time) must submit a petition requesting permission to do so. Student records will be reviewed to determine whether a student is taking this course for a three or more times. Any such student must return an approvedpetition to the instructor within the first two weeks of class. Any student who does not submit an approved petition will be dropped from the class. Petitions are available in the Department office (RVR 3018) and require the signature of both the Instructor and the Dept. Chair.
LECTURE CLASS MEETS: TR 9-1015A LIB 127 (Ghansah)
LABORATORY CLASS MEETS: R 1030-1 RVR 3009 (Ghansah)
TEXTBOOKS:
- B. Brey, Intel Microprocessors, 6 Ed, Prentice Hall, 2005
- I. Ghansah, C pE 185 Class Notes, 2005, Online(Required)
- T. Shanley, Protected Mode Software Architecture, Addison Wesley, 1996
- W. Triebel, The 80386, 80468, and Pentium Processor: Hardware, Software, and Interfacing, Prentice Hall 1998 (Required)
- Uffenbeck, The 80x86 Family, 3Ed, Prentice Hall, 2002
- K. Irvine, Assembly Language for Intel-based Computers 4 Ed., Prentice Hall 2003
- Intel, Intel Architecture Software Developer’s Manual, Vol 1: Basic Architecture, , Vol 2: Instruction SetReference ; Vol 3: System Programming Guide, 1997. ( )
- Mazdi and Mazdi, The Intel 86 IBM PC and Compatible Computers (Vols. I and II), 2Ed, Prentice Hall, 1998
REFERENCES:
Data Sheets for Peripherals such as:
- 82C55A Programmable Peripheral (parallel) Interface (PPI), 8250/16450/16550 UART, 82C54 Programmable Interval Timer, 82C59A Programmable Interrupt Controller
2.Recent Articles from the technical literature and product information from manufacturer’s literature
COURSE OBJECTIVES:
1.To provide students with an in-depth understanding of the function and specifications of the hardware devices that interface to a computer, and familiarity with the language and vocabulary used to describe those devices.
2.To provide an understanding of the organization of those devices.
- To provide an understanding and appreciation of the hardware/software interface, and the design of both real-mode and protected-mode programs that span the hardware/software interface.
- To provide an understanding of how microprocessors interface to their peripherals.
PREREQUISITES BY TOPIC:
Assembly language programming proficiency, Data representation, Logic Design, and C Programming language proficiency
Course Outcomes:
CpE 185 CO_1 Students will design a microprocessor memory interface at the hardware level.
CpE 185 CO_2 Students will understand a variety of input/output hardware interfaces to a microprocessor.
CpE 185 CO_3 Students will be able to design software code for hardware interfaces and they will understand tradeoffs between hardware and software when designing systems at the interface level.
CpE 185 CO_4 Students will acquire hands-on laboratory skills (design, coding, testing, debugging techniques) as well as learn to use appropriate tools for system development.
CpE 185 CO_5 Students will write technical reports.
HOMEWORK: will consist of lecture assignments and lab experiment (programming assignment) write-ups to hand in. There might also be homework assignments you are not required to hand in. Late work will lose credit. Although you are encouraged to discuss your designs with others, each student must do his/her own work in both lecture and lab. Submitting work in either is a contractual agreement that the work is the student’s own and for which he/she may be quizzed in detail. All assignments must be completed satisfactorily to pass the course. To be successful in getting homework done on time, it is important to be attentive in class, study your class notes, and read the assigned pages in your text book.
Design (Laboratory) assignments: A major portion of this course will be “software” design assignments done on the Intel Architecture based systems in the computer engineering laboratories. Lectures will cover the hardware and software design concepts of many types of computer interfaces. Students will then use some of these interfaces (already built up in the lab) in their software design (lab) solutions. A lab report must be turned in to the lab instructor a week after the demonstration. No lab assignments will be accepted during the lecture period. No hard copy lab reports should be placed in my mailbox. If you do, it will be ignored. I will only accept a copy (cc) of your lab report (for informational purposes only) in electronic form as specified below under the section ‘electronic communication’.
Advise on Workload and Class Notes for CpE 185: Please be advised that there is a lot of work in this class. There will be work during the scheduled laboratory session every week. However, there will be programming assignments that you might not be able to finish during the scheduled laboratory periods. You expect to put in a considerable amount of time at the computers outside of scheduled labs. As a practical matter, you should plan to use the lab time for minor debugging and demonstration. The class notes you will print from the website should be considered as a guide. Many parts of it are not detailed enough to be self-contained. In addition, experience shows that new material is added every semester. Therefore, attendance to class is necessary in order to understand the details.
GRADING POLICY:
Midterm25%
Final32%
Laboratory38%
Homework5%
Grading Breakdown (%):
A = 93-100C = 73-76
A- = 90-92C- = 70-72
B+ = 87-89D+ = 67-69
B = 83-86D = 63-66
B- = 80-82D- = 60-62
C+ = 77-79F = 59 or below
You must pass both the lab assignments and the exams in order to obtain a passing grade for the course.Students are required to keep backup (machine-readable) copies of all submitted work, and also to keep all returned (graded) work, until after final grades are posted.
ELECTRONIC COMMUNICATION:
a) gaia account
To facilitate secure electronic communication every student must have get an account on gaia. If you do not have gaia account you can obtain one by going to the College website: or by obtaining one from the College IT staff in room 2011. For both security reasons and convenience all email to me must be sent from that account. The College has a web-based email system on gaia ( gaia.ecs.csus.edu/mail ) that you can use for email. You must also use your gaia account for subscribing to the class mailing list which is described below.
b) Mailing List
I have established a Mailing List for this course. It is MANDATORY for every student accepted into the course to subscribe to the Mailing List within the first two weeks of classes. The list will be used to facilitate electronic communication for the course. Failure to subscribe to the list in a timely manner could result in your missing important assignments, clarifications, announcements, etc that are sent by email. You must email on a regular bases and I will assume that you have received and read all messages I send to the list. The instructor will not be held responsible for your failures. To subscribe to the list from send the following email message to
Subscribe cpe185
end
This will add your email address (the one from which you send the message, hopefully gaia) to the cpe185 mailing list. Subsequently you can send questions or discussion items regarding topics in cpe185 to everyone on the list. To do this, just send an email message to the address “”. This is a good way to other students in the class clarifications about assignments, lecture, etc. Note that these email messags are sent to everyone on the cpe185 list (including the instructors). If you need to communicate privately with the Instructor, use the Instructor’s individual email address as given above.
To make sure that your gaia account is used for subscription to the mailing list you must send the email from gaia.I will check the list from time to time to determine who is registered. If I notice any email address other than one from gaia, I will delete it.
c) Assignment/Homework Submission
You must submit all homework/assignments/project reports electronically as an email attachment. I will not accept a hardcopy. The attached file should be a Word document and must have a name according to one of the following formats (depending on the type of assignment). Your email should be sent to grader/lab instructor (if one is assigned) with copy to me. If no grader/lab instructor is assigned for the course email your submission to me.
Your-name_course#_hmwk _hmwk#, your-name_course#_lab_lab#, your-name_course_project_project#
For example if a student named John Doe is submitting homework#1 the file name of the email attachment should bedoe-john_185_hmwk_1
Please note: If the attachment is not according to proper format as stated above, it will not be accepted.
COURSE POLICIES:
1. Information in this syllabus is subject to change with notice.
2.Attendance to class and frequent check of email is expected. Class roll will not be checked after first week of classes. However, you are responsible for material presented and announcements made in class or by email. This could include changes to the syllabus, exam dates, etc.
3.Late assignment/project will be penalized by 20% if one lecture late.
Nothing will be accepted if more than one lecture late, or if solution has been posted.
4.Make-up exams will only be given under extreme circumstances. The instructor reserves the right to reject make-up requests.
5.Be aware of the institution policy on drops and incomplete.
Ethics/Academic Dishonesty
Any work submitted is a contractual obligation that the work is the student’s and for which he/she could be quizzed in detail.Discussion among students in assignments and projects is part of the educational process and is encouraged. No discussion among students is allowed in any exams/quizzes. However, each student must make an effort to do his/her own work in all assignments and exams. No type of plagiarism will be tolerated except in the case of group work. In that case each student should indicate the part of the work, which was their major responsibility in their final joint submission. Nevertheless, I emphasize any work submitted is a contractual obligation that the work is the student’s and for which he/she could be quizzed in detail. The minimum penalty for even a single incident of cheating brought to the attention of the instructor in this course is automaticfailure of the course; additional more severe penalties may also be applied. Note that cheating is grounds for dismissal from the University.
Please refer to the Computer Science Dept. document entitled “Policy on Academic Integrity” (available online via the Computer Science department, home page) and to the University Policy Manual section on Academic Honesty (all available online via the instructor’s home page) for additional information. IT IS THE RESPONSIBILITY OF EACH STUDENT TO BE FAMILIAR WITH, AND TO COMPLY WITH, THE POLICIES STATED IN THESE DOCUMENTSIn addition, unless otherwise stated, the use of the following devices during exams/quizzes is prohibited: cell phones, pagers, laptops, and PDAs.
CPE 185 - TENTATIVE SCHEDULE
Week / SUBJECT MATTER / READING1 / Introduction to Microprocessor Systems / Triebel-Ch. 1&2; Intel Arch. Vol 1
Brey Ch 1-6;
2 / Intel Microprocessor Family., x86, Pentium family. / Triebel- Ch 3-7;Intel Arch. Vol 1&2. Brey Ch 9;
3 / Memory Interfacing, Wait State Generators, Watchdog Timers, etc. / Triebel- p372-419; 440-496; Brey Ch 10 & 17
4 / Input-Output. Programmed I/O. Software (BIOS/DOS) Interrupts. / Class Notes, Triebel- p419-435. Brey Ch 11
5 / Keyboard Interfacing. Keyboard Controller / Triebel-Ch. 11; Brey-Ch. 11
6 / I/OPort Addressing. Memory-mapped and Isolated I/O. Programmed I/O. / Triebel Ch. 11; Brey Ch. 11;
7-8 / Interrupts. Hardware and Software considerations. i8259 Programmable Interrupt Controller (PIC) / Triebel- Ch.12; Brey- Ch.12;
Mar. 13-17 / SPRING BREAK / SPRING BREAK
9 / Serial I/O. RS 232C. 8250/16450/16550 UART and SerialPort.
Programmable Interval Timers / Triebel Ch. 11; Brey p 439-447
10-12 / Protected ModeArchitecture.
Segment Descriptors, Descriptor Tables, Privilege levels, Call Gates, Interrupt Gates / Triebel Ch. 8; Intel Arch. Vol. 3; p59-67; p688-716
13 / Direct Memory Access. 8237 DMA Controller.
Programmable Interval Timers / Triebel- Sec 11.9&11.10; Brey Ch 13
14 / Buses. Control and Arbitration Protocols. Standards and Examples.
ISA Bus, PCI Bus, Nu Bus, SCSI, USB, etc. / Class Notes; Triebel Ch. 14 ; Brey Ch 14;
15 / Intel Architectural Evolution. 8, 16, 32, and 64 bit systems (+ Itanium) / Brey Ch 17-19
16 / FINAL EXAM (M 5/15/06, 8A-10A?)
IMPORTANT DATE: Caesar Chavez Birthday: F 3/31
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