Introduction

Flip-flops are synchronous bistable devices. The term synchronous means the output changes state only when the clock input is triggered. That is, changes in the output occur in synchronization with the clock.

Flip-flop is a kind of multivibrator. There are three types of multivibrators:

  1. Monostable multivibrator (also called one-shot) has only one stable state. It produces a single pulse in response to a triggering input.
  2. Bistable multivibrator exhibits two stable states. It is able to retain the two SET and RESET states indefinitely. It is commonly used as a basic building block for counters, registers and memories.
  3. Astable multivibrator has no stable state at all. It is used primarily as an oscillator to generate periodic pulse waveforms for timing purposes.

In this tutorial, the three basic categories of bistable elements are emphasized: edge-triggered flip-flop, pulse-triggered (master-slave) flip-flop, and data lock-out flip-flop. Their operating characteristics and basic applications will also be discussed.

Edge-Triggered Flip-flops

An edge-triggered flip-flop changes states either at the positive edge (rising edge) or at the negative edge (falling edge) of the clock pulse on the control input. The three basic types are introduced here: S-R, J-K and D.

/ Click on one the following types of flip-flop. Then
its logic symbol will be shown on the left. Notice the
small triangle, called the dynamic input indicator, is
used to identify an edge-triggered flip-flop.
Positive edge-triggered (without bubble at Clock input):
S-R, J-K, and D.
Negative edge-triggered (with bubble at Clock input):
S-R, J-K, and D.

The S-R, J-K and D inputs are called synchronous inputs because data on these inputs are transferred to the flip-flop's output only on the triggering edge of the clock pulse.On the other hand, the direct set (SET) and clear (CLR) inputs are called asynchronous inputs, as they are inputs that affect the state of the flip-flop independent of the clock. For the synchronous operations to work properly, these asynchronous inputs must both be kept LOW.

Edge-triggered S-R flip-flop

The basic operation is illustrated below, along with the truth table for this type of flip-flop. The operation and truth table for a negative edge-triggered flip-flop are the same as those for a positive except that the falling edge of the clock pulse is the triggering edge.

As S = 1, R = 0. Flip-flop SETS on the rising clock edge.

Note that the S and R inputs can be changed at any time when the clock input is LOW or HIGH (except for a very short interval around the triggering transition of the clock) without affecting the output. This is illustrated in the timing diagram below:

Edge-triggered J-K flip-flop

The J-K flip-flop works very similar to S-R flip-flop. The only difference is that this flip-flop has NO invalid state. The outputs toggle (change to the opposite state) when both J and K inputs are HIGH. The truth table is shown below.

Edge-triggered D flip-flop

The operations of a D flip-flop is much more simpler. It has only one input addition to the clock. It is very useful when a single data bit (0 or 1) is to be stored. If there is a HIGH on the D input when a clock pulse is applied, the flip-flop SETs and stores a 1. If there is a LOW on the D input when a clock pulse is applied, the flip-flop RESETs and stores a 0. The truth table below summarize the operations of the positive edge-triggered D flip-flop. As before, the negative edge-triggered flip-flop works the same except that the falling edge of the clock pulse is the triggering edge.

Pulse-Triggered (Master-Slave) Flip-flops

The term pulse-triggered means that data are entered into the flip-flop on the rising edge of the clock pulse, but the output does not reflect the input state until the falling edge of the clock pulse. As this kind of flip-flops are sensitive to any change of the input levels during the clock pulse is still HIGH, the inputs must be set up prior to the clock pulse's rising edge and must not be changed before the falling edge. Otherwise, ambiguous results will happen.
The three basic types of pulse-triggered flip-flops are S-R, J-K and D. Their logic symbols are shown below. Notice that they do not have the dynamic input indicator at the clock input but have postponed output symbols at the outputs.

The truth tables for the above pulse-triggered flip-flops are all the same as that for the edge-triggered flip-flops, except for the way they are clocked. These flip-flops are also called Master-Slave flip-flops simply because their internal construction are divided into two sections. The slave section is basically the same as the master section except that it is clocked on the inverted clock pulse and is controlled by the outputs of the master section rather than by the external inputs. The logic diagram for a basic master-slave S-R flip-flop is shown below.

Data Lock-Out Flip-flops

The data lock-out flip-flop is similar to the pulse-triggered (master-slave) flip-flop except it has a dynamic clock input. The dynamic clock disables (locks out) the data inputs after the rising edge of the clock pulse. Therefore, the inputs do not need to be held constant while the clock pulse is HIGH.
The master section of this flip-flop is like an edge-triggered device. The slave section becomes a pulse-triggered device to produce a postponed output on the falling edge of the clock pulse.
The logic symbols of S-R, J-K and D data lock-out flip-flops are shown below. Notice they all have the dynamic input indicator as well as the postponed output symbol.

Again, the above data lock-out flip-flops have same the truth tables as that for the edge-triggered flip-flops, except for the way they are clocked.

Operating Characteristics

The operating characteristics mention here apply to all flip-flops regardless of the particular form of the circuit. They are typically found in data sheets for integrated circuits. They specify the performance, operating requirements, and operating limitations of the circuit.
Propagation Delay Time - is the interval of time required after an input signal has been applied for the resulting output change to occur.

Set-Up Time - is the minimum interval required for the logic levels to be maintained constantly on the inputs (J and K, or S and R, or D) prior to the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip-flop.

Hold Time - is the minimum interval required for the logic levels to remain on the inputs after the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip-flop.

Maximum Clock Frequency - is the highest rate that a flip-flop can be reliably triggered.

Power Dissipation - is the total power consumption of the device.

Pulse Widths - are the minimum pulse widths specified by the manufacturer for the Clock, SET and CLEAR inputs.

Applications

Frequency Division

When a pulse waveform is applied to the clock input of a J-K flip-flop that is connected to toggle, the Q output is a square wave with half the frequency of the clock input. If more flip-flops are connected together as shown in the figure below, further division of the clock frequency can be achieved.

The Q output of the second flip-flop is one-fourth the frequency of the original clock input. This is because the frequency of the clock is divided by 2 by the first flip-flop, then divided by 2 again by the second flip-flop. If more flip-flops are connected this way, the frequency division would be 2 to the power n, where n is the number of flip-flops.

Parallel Data Storage

In digital systems, data are normally stored in groups of bits that represent numbers, codes, or other information. So, it is common to take several bits of data on parallel lines and store them simultaneously in a group of flip-flops. This operation is illustrated in the figure below.

/ Each of the three parallel data lines is connected to the D input of a flip-flop. Since all the clock inputs are connected to the same clock, the data on the D inputs are stored simultaneously by the flip-flops on the positive edge of the clock. Registers, a group of flip-flops use for data storage, will be explained in more detail in a later chapter.

Counting

Another very important application of flip-flops is in digital counters, which are covered in detail in the next chapter.
A counter that counts from 0 to 3 is illustrated in the timing diagram on the right. The two-bit binary sequence repeats every four clock pulses. When it counts to 3, it recycles back to 0 to begin the sequence again. /

Introduction

Circuits for counting events are frequently used in computers and other digital systems. Since a counter circuit must remember its past states, it has to possess memory. The chapter about flip-flops introduced how flip-flops are connected to make a counter. The number of flip-flops used and how they are connected determine the number of states and the sequence of the states that the counter goes through in each complete cycle.

Counters can be classified into two broad categories according to the way they are clocked:

  1. Asynchronous (Ripple) Counters - the first flip-flop is clocked by the external clock pulse, and then each successive flip-flop is clocked by the Q or Q' output of the previous flip-flop.
  2. Synchronous Counters - all memory elements are simultaneously triggered by the same clock.

In this tutorial, pure binary, decade and up-down counters within the two categories will be introduced.

Asynchronous(Ripple) Counters

/ A two-bit asynchronous counter is shown on the left. The external clock is connected to the clock input of the first flip-flop (FF0) only. So, FF0 changes state at the falling edge of each clock pulse, but FF1 changes only when triggered by the falling edge of the Q output of FF0. Because of the inherent propagation delay through a flip-flop, the transition of the input clock pulse and a transition of the Q output of FF0 can never occur at exactly the same time. Therefore, the flip-flops cannot be triggered simultaneously, producing an asynchronous operation.

Note that for simplicity, the transitions of Q0, Q1 and CLK in the timing diagram above are shown as simultaneous even though this is an asynchronous counter. Actually, there is some small delay between the CLK, Q0 and Q1 transitions.

Usually, all the CLEAR inputs are connected together, so that a single pulse can clear all the flip-flops before counting starts. The clock pulse fed into FF0 is rippled through the other counters after propagation delays, like a ripple on water, hence the name Ripple Counter.

The 2-bit ripple counter circuitabove has four different states, each one corresponding to a count value. Similarly, a counter with n flip-flops can have 2 to the power n states. The number of states in a counter is known as its mod (modulo) number. Thus a 2-bit counter is a mod-4 counter.

A mod-n counter may also described as a divide-by-n counter. This is because the most significant flip-flop (the furthestflip-flop from the original clock pulse) produces one pulse for every n pulses at the clock input of the least significant flip-flop (the one triggers by the clock pulse). Thus, the above counter is an example of a divide-by-4 counter.

The following is a three-bit asynchronous binary counter and its timing diagram for one cycle. It works exactly the same way as a two-bit asynchronous binary counter mentioned above, except it has eight states due to the third flip-flop.

AsynchronousDecade Counters

The binary counters previously introduced have two to the power n states. But counters with states less than this number are also possible. They are designed to have the number of states in their sequences, which are called truncated sequences. These sequences are achieved by forcing the counter to recycle before going through all of its normal states.

A common modulus for counters with truncated sequences is ten. A counter with ten states in its sequence is called adecade counter. The circuit below is an implementation of a decade counter.

Once the counter counts to ten (1010), all the flip-flops are being cleared. Notice that only Q1 and Q3 are used to decode the count of ten. This is called partial decoding, as none of the other states (zero to nine) have both Q1 and Q3 HIGH at the same time.

The sequence of the decade counter is shown in the table below:

AsynchronousUp-Down Counters

In certain applications a counter must be able to count both up and down. The circuit below is a 3-bit up-down counter. It counts up or down depending on the status of the control signals UP and DOWN. When the UP input is at 1 and the DOWN input is at 0, the NAND network between FF0 and FF1 will gate the non-inverted output (Q) of FF0 into the clock input of FF1. Similarly, Q of FF1 will be gated through the other NAND network into the clock input of FF2. Thus the counter will count up.

When the control input UP is at 0 and DOWN is at 1, the inverted outputs of FF0 and FF1 are gated into the clock inputs of FF1 and FF2 respectively. If the flip-flops are initially reset to 0's, then the counter will go through the following sequence as input pulses are applied.

/ Notice that an asynchronous up-down counter is slower than an up counter or a down counter because of the additional propagation delay introduced by the NAND networks.

Synchronous Counters

In synchronous counters, the clock inputs of all the flip-flops are connected together and are triggered by the input pulses. Thus, all the flip-flops change state simultaneously (in parallel). The circuit below is a 3-bit synchronous counter. The J and K inputs of FF0 are connected to HIGH. FF1 has its J and K inputs connected to the output of FF0, and the J and K inputs of FF2 are connected to the output of an AND gate that is fed by the outputs of FF0 and FF1.

Pay attention to what happens after the 3rd clock pulse. Both outputs of FF0 and FF1 are HIGH. The positive edge of the 4th clock pulse will cause FF2 to change its state due to the AND gate.

/ The count sequence for the 3-bit counter is shown on the right.
The most important advantage of synchronous counters is that there is no cumulative time delay because all flip-flops are triggered in parallel. Thus, the maximum operating frequency for this counter will be significantly higher than for the corresponding ripple counter.

SynchronousDecade Counters

Similar to an asynchronous decade counter, a synchronous decade counter counts from 0 to 9 and then recycles to 0 again. This is done by forcing the 1010 state back to the 0000 state. This so called truncated sequence can be constructed by the following circuit.

/ From the sequence on the left, we notice that:
  • Q0 toggles on each clock pulse.
  • Q1 changes on the next clock pulse each time Q0=1 and Q3=0.
  • Q2 changes on the next clock pulse each time Q0=Q1=1.
  • Q3 changes on the next clock pulse each time Q0=1, Q1=1 and Q2=1 (count 7), or when Q0=1 and Q3=1 (count 9).

These characteristics are implemented with the AND/OR logic connected as shown in the logic diagram above.

SynchronousUp-Down Counters

A circuit of a 3-bit synchronous up-down counter and a table of its sequence are shown below. Similar to an asynchronous up-down counter, a synchronous up-down counter also has an up-down control input. It is used to control the direction of the counter through a certain sequence.

/ An examination of the sequence table shows:
  • for both the UP and DOWN sequences, Q0 toggles on each clock pulse.
  • for the UP sequence, Q1 changes state on the next clock pulse when Q0=1.
  • for the DOWN sequence, Q1 changes state on the next clock pulse when Q0=0.
  • for the UP sequence, Q2 changes state on the next clock pulse when Q0=Q1=1.
  • for the DOWN sequence, Q2 changes state on the next clock pulse when Q0=Q1=0.

These characteristics are implemented with the AND, OR & NOT logic connected as shown in the logic diagram above.

Applications

Digital counters are very useful in many applications. They can be easily found in digital clocks and parallel-to-serial data conversion (multiplexing). In this section, we will use the later as an example on how counters are being used.