CEG 360/560 – EE 451/651 Lab 4
Dr. Doom
Lab 4: A Simple Computer Architecture
CEG 360/560 - EE 451/651
PURPOSE
The purpose of this lab is to design and build - using B2-Logic - a circuit that simulates a simple microprocessor and memory system. Fundamentally, a microprocessor has two major components: a data unit and a control unit. In this lab, we will build (bottom-up) a simple multiple-cycle microprocessor with a micro-programmed control using implicit sequencing. This is a three-week final project.
OVERVIEW
The microprocessor has the inputs and outputs shown above and described below:
CLOCK: The external clock signal for the synchronous system.
RESET: A 1-bit value that resets the computer to its idle/ready state when asserted.
READY: A 1-bit output that is asserted high only when the microprocessor is in the idle state and awaiting a new instruction.
START: A 1-bit value that must be asserted for one clock tick to instruct the computer to execute a new INSTRUCTION.
INSTRUCTION: A 16-bit value representing a computer operation. The value of INSTRUCTION must be held stable from the beginning of its execution (the assertion of START) to the end of its execution (the assertion of READY).
ADDRESS OUT: A 4-bit output that provides the binary address of a desired memory word.
DATA IN: A 4-bit input that accepts a data word from memory.
DATA OUT: A 4-bit output that provides a data word to be stored in memory.
WRITE ENABLE: A 1-bit output that enables a memory write.
Upon initialization (via the RESET input) the microprocessor asserts READY and awaits its first instruction. Once the instruction is stable, the external system must assert START to indicate that the instruction should be executed. READY is disserted while the microprocessor executes the given operation. Once finished, the microprocessor asserts READY and awaits its next instruction.
This simple computer has a very small instruction set. Furthermore, the instructions are very basic; the microprocessor is not required to maintain any state information between instructions. Thus, the results of each instruction depend only upon the current contents of the RAM and modify only the RAM. In other words, the ISA for this machine consists of memory-to-memory operations only.
The 16-bit instruction is composed of four 4-bit fields:
15-12 / 11-8 / 7-4 / 3-0OPCODE / OPERAND A / OPERAND B / OPERAND C
The OPCODE field defines the type of operation to be performed. The OPERAND values provide the data that exactly specifies the operation. The microprocessor supports the following instructions:
OPCODE / FUNCTION / OPCODE / FUNCTION0 / NOP/IDLE / 5 / M[C] ß M[A] + M[B]
1 / M[C] ß M[A] / 6 / M[C] ß M[A] - M[B]
2 / M[C] ß M[A] + B / 7 / IF (M[A] = 0) THEN M[C] ß M[B]
3 / M[C] ß A / 8 / IF (M[A] < M[B]) THEN M[C] ß 0
ELSE M[C] ß 1
4 / M[C] ß sr(M[A])
Example: The 16-bit instruction x3803 specifies the operation M[x3] ß x8 (i.e. the microprocessor must write the value x8 into the RAM word specified by the address x3).
This system is moderately complex, thus it will be advantageous to decompose the design into less complex entities. A data unit will be constructed which is capable of performing several basic microoperations. In order to standardize the design of this project, we will use the datapath described in Mano, Ch. 7. A control unit will then be constructed which is capable of sequencing the data unit through the microoperations necessary to perform the instruction given to the microprocessor.
PRELAB (WEEK ONE): Datapath Construction
(10 pts.) The goal of the first week is to implement the datapath shown in Figure 7-9) and described in sections 7-6 to 7-9. The datapath consists of two primary components (a register files and a function unit) and the glue logic between them.
1) The first primary component is a 4 x 4 register file with a dual-ported read and a single write port. In other words, this device contains four 4-bit general purpose registers for which two read and one write operation can be performed simultaneously. Numeric values contained in these registers are represented as signed magnitude numbers (Mano, ch. 3). This device can be implemented using four 4-bit registers, two 4-bit 4-to-1 line multiplexers, a 2-to-4 decoder, and four AND gates (as shown in Figure 7-9).
a) The readability of our design will be greatly simplified if we create "block diagrams" of our multiplexers as library macros. Construct a 4-bit 2-to-1 multiplexer using the 2-to-1 multiplexer (M2_1) in the XC4000E library. Your design should accept two 4-bit inputs (labeled 0IN[3:0] and 1IN[3:0]), one 1-bit select input (labeled SEL), and produce one 4-bit output (labeled MUX[3:0]). Save the circuit as a macro in your project library. Include a printout and simulation in your lab book.
b) Construct a 4-bit, 4-to-1 multiplexer using the same conventions (inputs labeled A, B, C, and D). Save the circuit as a macro. Include a printout and simulation in your lab book.
Implement the 4 x 4 dual-ported read register file in the Foundation schematic editor using instances of your user defined 4-bit multiplexers and other logic as necessary. Label the inputs of the register file CLK, WRITE (for Load enable), A_ADR (for A select), B_ADR (for B select), D_ADR (for Destination select), and D_DATA. Label the four-bit outputs A_DATA and B_DATA. Save the circuit as a macro to your project library. Include a printout and simulation in your lab book.
2) The second primary component of the datapath is a function unit capable of performing the operations listed in Table 7-10. These functions can be implemented by constructing two functional units: a 4-bit ALU and a 4-bit Shifter. You will need to copy the ALU files and macros constructed in Lab #1 to your current project library.
a) Implement a basic 4-bit combinational shifter using multiplexers (see Figure 7-16). Assume that the incoming bit (the bit shifted in) is always 0. The shifter has a four-bit input B[3:0], a two-bit select S[1:0], and a four-bit output H[3:0]. Save the circuit as a macro. Include a printout and simulation in your lab book.
b) Implement the function unit (as shown in Figure 7-9) using your ALU, shifter, and the appropriate multiplexers as user-defined circuits. The function unit should be implemented with a two 4-bit inputs A and B as well as a 4-bit select input G_SELECT, a 2-bit select input H_SELECT, and a 1-bit select MF Select. Include necessary circuitry to provide the status bits V, C, N, and Z (consult page 358). Verify that your circuit implements the functionality described in Table 7-10 and include a copy of your logic diagram in your lab book, as well as a simulation. Save the circuit to your library as a macro.
3) Implement the datapath using your 4 x 4 register file, your function unit, and appropriate multiplexer logic (consult Figure 7-9).
a) You will need to provide a 14-bit input for the control word as well as two 4-bit inputs: Constant In (CONST[3:0] and Data In [DATA_IN[3:0]. A single-bit input CLOCK should be used as the clock signal for the register file. The datapath has three 4-bit outputs: Address Out (ADR_OUT[3:0]), Data Out (DATA_OUT[3:0]), and the status signals VNCZ.
The fields for the 14-bit datapath control words are defined as follows:
13-12 / 11-10 / 9-8 / 7 / 6-2 / 1 / 0DA (2) / AA (2) / BA (2) / MB (1) / FS (5) / MD (1) / RW (1)
b) Use bus logic to decode the control word into the RW, DA, AA, BA, MB, and MD signals required by your previously specified devices. Also include the 5-bit input FS and the logic necessary to decode FS into MF select, G select, and H select as shown in Table 7-10. Connect Constant In, Data In, Address Out, and Data Out as shown in Mano, Figure 7-19.
4) Verify that circuit implements the correct functionality and include a copy of your logic diagram, simulation and test procedure documentation in your lab book.
5) Assume that all words in RAM memory are initialized to x0. In your lab notebook, show the expected results (i.e. the contents of RAM memory) of the execution of the following sequence of microprocessor instructions: x3450, x4000, x2021. Remember these words are instructions to the microprocessor not control words to the datapath
6) Note that none of the microprocessor instructions directly access the registers in the datapath. The ISA for this machine consists of memory-to-memory operations only. We will, however, need to use the registers in our datapath to perform these instructions through a sequence of microoperations. Since the “external system” cannot directly access our registers we are free to use all four of them as scratch (temporary) registers during the micro-routine for each instruction. For each of the microprocessor instructions given above in 5), determine a sequence of datapath microoperations that implement the specified microprocessor instruction.
Graduate students only: Graduate students are expected to implement a pipelined datapath (consult Mano, ch. 7-11 and refer to Figure 7-23). The pipeline is worth 5 of the pre-lab points for graduate students: 2.5 points for week one, 2.5 points for week 2. The final circuit must be pipelined in order to receive in-lab points for week 3.
IN-LAB (WEEK ONE)
(5 pts.) Demonstrate your datapath implementation to your lab instructor. Be prepared to answer questions about the datapath such as “What microoperation is implemented for a given datapath control word” (consult Tables 7-11 and 7-12), and “What change should we expect to see in the registers for this microoperation”. Demonstrate the functionality of your datapath on for a sequence of microoperations such as those created in 6), above.
PRELAB (WEEK TWO): Control Unit Design
(10 pts.) The goal of the final two weeks of laboratory is to complete the implementation of the multi-cycle computer by implementing a control unit and memory subsystem. The control unit for this computer will be a non-programmable microprogrammed control with implicit sequencing. In other words, the control unit does not have a program counter; the instructions that it needs to execute next are provided to it by the external system. Each of the instructions to the computer, however, will require the execution of a sequence of microoperations. The microoperations performed for each instruction will be determined based upon the contents a microprogram in the control store. Unless the contents of the control word explicitly contain a branch the next instruction will be the next address in the control store (e.g. implicit addressing). In this lab, students will design a control address register (CAR), a control store, and decoding logic for the control unit and then design the microprogram (a process known as microcoding).
The control unit will use the inputs for INSTRUCTION, START, RESET, CLK, and the datapath status bits V, N, C, and Z. The control unit will have outputs for READY, MW, CONSTANT_OUT, and the datapath control word.
The primary components of the control unit are a control store and the control address register (CAR). The control store is a ROM containing the microinstructions for the control unit. These microinstructions determine the sequence of microoperations performed by the data unit. The CAR contains an address that is used as the input to the control store to select the “current" microinstruction. The logic that generates the data and load signals for the CAR controls the sequencing of the control unit microinstructions.
The architects for this system have defined the IDLE state to be the state in which CAR = x00. When CAR contains the value x00, READY should be asserted and the control unit should begin the processing of a new instruction when START is asserted. The microroutine for each instruction will begin at address OPCODE(7:4)0000 (i.e. The microprogram for the instruction with opcode E should begin at control store address xE0, where the opcode value is taken from the 4 most significant bits of the Instruction).
The architects for this system have determined that this computer will use a 256-address control store and have defined two classes of microinstruction. Each class of microinstruction will decode the microinstruction fields in a different way. This is advantageous as it decreases the number of bits required for each microinstruction (and therefore decreases the necessary size of the ROM). The MSB of the microinstruction (bit 15) will be used as a MODE bit to indicate the type of instruction and aid in the decoding.
The first class of microinstruction will be used to control the datapath by determining the control signals outputs of the unit. In addition, the LSB of the microinstruction (MW: Memory Write) will be used to control the Write Enable output of the control unit .
The second class of microinstruction will be branch instructions used to perform the explicit sequencing of the control unit. The branch microinstruction consists of two fields. The first is a 3-bit field CONDITION and the second is a 8-bit field NEXT_ADDRESS (note that this is sufficient to select any address in the control store). If the condition specified by CONDITION is true then the microinstruction at NEXT_ADDRESS must be executed next (CAR ß NEXT_ADDRESS) otherwise the next microinstruction is implicitly chosen (CAR ß CAR + 1).