8-by-8 Bit Booth Multiplier
by
Xing Chen Xin Xie
ID:5642671 5585740
A Project Report
submitted in partial fulfillment
of the requirements of
COEN 6501
Instructor: Dr. Asim J. Al-Khalili
ConcordiaUniversity
Dec 2006
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Abstract
This project describes the design of an 8 bit Multiplier A*B circuit using Booth Multiplication. The multiplier receives operands A and B, and outputs result Z. After registering operand A and B, load A to Booth Algorithm Block.Then use Booth algorithm to transform A and multiply by B. The output Z is the result of the original A*B.
Booth algorithm and architecture of the design are presented in details.In order to realize the multiplier, VHDL is introduced.The tests of the circuit show that the design can completelyaccord with different cases.
Timing and expand the circuit to high order like 16 by 16 bit multiplier will be also discussed in this paper.
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Table of Contents
1. INTRODUCTION
2. BOOTH ALGORITHM
3. IMPROVEMENT METHODOLOGY
4. STRUCTURE DESIGN
4.1 The Overview of Whole Structure of Booth Multiplier
4.2 The Structure of D Flip-Flop
4.2.1 The Structure of 1 Bit D Flip-Flop
4.2.2 The Structure of 8 Bit D Flip-Flop
4.2.3 The Structure of 16 Bit D Flip-Flop
4.3 The Structure of Booth Multiplier
4.3.1 Basic cells
4.3.2 Intermediated Block
4.3.3 Advanced Encapsulated Block
5. CIRCUIT TESTING
5.1 The Stimulator
5.2 The Test Bench
5.3 The Waveform of the Test Result
6. TIMING ANALYSIS
7. EXPANSION OF THE PROJECT
7.1 Register Expansion
7.2 Multiplier Expansion
8. CONCLUSION
APPENDIX A: BOOTH MULTIPLIER VHDL CODE
APPENDIX B: TEST BENCH VHDL CODE
APPENDIX C: LIST OF FIGURES
APPENDIX D: LIST OF TABLES
REFERENCES
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1. INTRODUCTION
Theobjection of this project is to design an 8 bit Multiplier A*B circuit using Booth Multiplication. The Multiplier can receive 8 bit signed number operands A & B, in a register RA and RB, and output the result in 16 bit register Z. In the beginning of each multiplication cycle, the operands (A & B) are loadedparallel in the RA and RB registers. Each multiplication starts with a LOAD signal and ends with an END signal.
Signal Specifications
A0-A7: Signed 8 bit Operand A
B0-B7: Signed 8 bit Operand B
Z0-Z15: Signed 16 bit Output
CLR: Clears selected registers
LOAD: Loads Operand into internal register
CLK: Clock input
END: End of Multiplying Signal
2. BOOTH ALGORITHM
As to the process of multiplying numbers, there are many algorithms to implement. In multiplying signed numbers together, special care is needed. Booth algorithm is an efficient means of multiplying signed numbers expressed in 2's complement notation. It is a powerful algorithm for signed-number multiplication, which treats both positive and negative numbers uniformly.
Booth algorithm is a method that is able to reduce the number of multiplicand multiples.This advantage can save both area and time in the circuit. For this project, the Radix-4 is used.
Table 1 is used to convert a binary number to Radix-4 number.Initially, a “0” is placed to the right most bit of the multiplier. Then 3 bits of the multiplicand is recoded according to the following equation. Equivalently, Table 1 maps the equation in details.
Xi+1 / X / Xi-1 / Zi/20 / 0 / 0 / 0
0 / 0 / 1 / 1
0 / 1 / 0 / 1
0 / 1 / 1 / 2
1 / 0 / 0 / -2
1 / 0 / 1 / -1
1 / 1 / 0 / -1
1 / 1 / 1 / 0
Table 1 Radix-4 Booth Recoding
The Multiplier bit-pair recoding is shown in Table 2.
0 / 0 / 0 / +0*multiplicand0 / 0 / 1 / +1*multiplicand
0 / 1 / 0 / +1*multiplicand
0 / 1 / 1 / +2*multiplicand
1 / 0 / 0 / -2*multiplicand
1 / 0 / 1 / -1*multiplicand
1 / 1 / 0 / -1*multiplicand
1 / 1 / 1 / -0*multiplicand
Table 2Multiplier Recoding
Here –2*multiplicand is actually the two’s complement of the multiplicand with an equivalent left shift of one bit position. Also, +2 *multiplicand is the multiplicand shifted left one bit position which is equivalent to multiplying by 2.
3. IMPROVEMENT METHODOLOGY
Usually, Booth Algorithm uses anN+1bit binary adder. A moreefficient way is to use only an Nbit binary adder. In such an algorithm, specialhandling is required for cases associated with two's complement overflow.
Another improvement is made by eliminating the Aregister, reusing part of the Zregister, to store the multiplier.
4. STRUCTURE DESIGN
4.1 The Overview of Whole Structure of Booth Multiplier
The entire structure of 8-by-8 bit Booth Multiplier is composed of three parts, shown in Figure 4.1. The first part is two 8 bit D Flip-Flops. The second is the heart of this project, Booth Multiplier. The last part is one 16 bit D Flip-Flop.
Figure 4.1The overview of Booth Multiplier
4.2 The Structure of D Flip-Flop
4.2.1 The Structure of 1 Bit D Flip-Flop
The 1 bit D Flip-Flop has four inputs including 1 bit D, cp(clk), clr, and load, and one output Q, shown in Figure 4.2.
Figure4.21 Bit D Flip-Flop Interface
4.2.2 The Structure of 8 Bit D Flip-Flop
The 8 bit D Flip-Flop includes 8 bits D, cp(clk), clr and load as the inputs, and 8 bit Qas output, shown in Figure 4.3.
Figure 4.38 Bit D Flip-Flop Interface
4.2.3 The Structure of 16 Bit D Flip-Flop
The 16 bit D flip-flop has inputs: 16 bits D, cp(clk), clr, and output:16bits Q. It does not need the load signal as the input. The function cansave the results when clk arriving and clk=’0', shown in Figure 4.4.
Figure 4.416 Bit D Flip-Flop Interface
4.3 The Structure of Booth Multiplier
The block diagram of Booth Multiplier is shown in Figure 4.5, where RA is the register of input A, RB is the register of input B, RZ is the output register, shifter is barrel shifter (shift left by 2 bits). Depending on the booth Radix-4 encoding rule, RA should be selected and shifted by 2, -2, 0. Also, depending on those values (2, 1, 0, -1, -2), control unit can choose the MUX output.
Figure 4.5Block Diagram of Booth Multiplier
4.3.1 Basic cells
Some basic cells are used to build the advanced modules of the design.
1.Gate Inverter: Input A; output Z is the inverse of A, shown in Figure 4.6.
Figure 4.61 bit Inverter
2. Gate And: inputsare A, B; output Z is A and B, shown in Figure 4.7
Figure 4.7AND Gate
3. Gate OR: inputsare A, B; output Z is A or B, shown in Figure 4.8.
Figure 4.8OR Gate
4. Gate XOR: built from gate Inverter, AND and OR, shown in Figure 4.9.
Figure 4.9XOR Gate
5. Half-Adder:input are A, B; output CRY, SUM, built from gate AND and XOR, shown in Figure 4.10.
Figure 4.10Half-Adder
6. Full-Adder: inputsare A, B, Cin; outputs are Cout, Z, built from Half-Adder and OR gate, shown in Figure 4.11.
Figure 4.11Full-Adder
7. MUX 2:1: inputsare A, B, SEL; output is Z. When SEL<=’1’, Z <= A, otherwise Z<=B, built from Gate Inverter, AND, and OR, shown in Figure 4.12.
Figure 4.12MUX 2:1
4.3.2 Intermediated Block
These blocks are built from the above cells.
- MUX 8:1: inputs are A, B, C, D, E, F, G, H, selection bit S0, S1, S2; output is Z, According to the selection Table 3. The structure is shown in Figure 4.13.
S0 / S1 / S2 / OUTPUT Z
0 / 0 / 0 / A
1 / 0 / 0 / B
0 / 1 / 0 / C
1 / 1 / 0 / D
0 / 0 / 1 / E
1 / 0 / 1 / F
0 / 1 / 1 / G
1 / 1 / 1 / H
Table 3 MUX 8:1 Selection Rule
Figure 4.13MUX 8:1
- Barrel Left Shift 1 bit: inputs are X(7 downto 0), selection S0; output is Y(7 downto 0).Its function is to calculate 2X, shown in Figure 4.14.
Figure 4.14Barrel Left 1 bit Shifter
- Booth Adder: inputs are X (7 downto 0),Y(7 downto 0) and Cin; outputis Z(7 downto 0), Cout. The function is a Cripple Carry adder, shown in Figure 4.15.
Figure 4.15Booth Adder
4.3.3Advanced Encapsulated Block
These blocks are introduced according to the architecture from top to bottom.
1. The top level entity:Block Multiplier. DFF0 is the register of input A (7 downto 0). DFF1 is the register of input B (7 downto 0). DFF2 is the register of output Z (15 downto 0). a0, a1, a2, a3, are the blocks of Partial_Product,their functions are to calculate the partial product,shown in Figure 4.16.
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Figure 4.16Block Multiplier Interface
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2. Patial_Product Block. The function is to calculate these partial products. It includes several blocks, shown in Figure 4.17.
Note:
Y_BAR: block to calculate minusY.
Two_Y: block to calculate 2*Y.
Two_YBAR: block to calculate minus 2*Y.
BOOTH: block of booth encoder according to multiplier encode rules.
a1: block of Booth_Adder introduced before.
a2: Full Adder
Figure 4.17Partial_Product Interface
5. CIRCUIT TESTING
This chapter will explain the verification strategy and result of the testing. A test bench is designed to verify the circuit.
5.1The Stimulator
The Stimulator creates the load <=’1’, clr = 0, clk, and A(7 downto 0), B(7 downto 0), using these signals to test the Multiplier, shown in Figure 5.1.
Figure 5.1 Stimulator Interface
5.2The Test Bench
It connects the output (load=1,clr=0,clk,A(7 downto 0) B(7 downto 0))of the stimulator with the input of the Multiplier. The structure of the Test-Bench consists of the Stimulator and the Multiplier, shown in Figure 5.2
Figure 5.2Structure of Test Bench
5.3The Waveform of the Test Result
There are four cases to test the circuit.
- load=1,clr=0,clk, A( 7 downto 0=”11111101”, B(7 downto 0)=”00000011”. The Test wave form shown in Figure 5.3. The cycle of clk is 40 ns. The delay of end1 means the end of calculation. The output Z shows the correct result.
Figure5.3Waveform of Case One
- load=1,clr=1,clk, A( 7 downto 0=”11111101”, B(7 downto 0)=”00000010”. From this case, we can see the clr=1 will reset all the D Flip-Flop.
Figure 5.4Waveform of Case Two
- load=0,clr=0,clk, A( 7 downto 0=”11111101”, B(7 downto 0)=”00000011”. From this case( load=0 ), the inputs will not be loaded, so there is no output.
Figure 5.5Waveform of Case Three
- load=1,clr=0,clk=0, A( 7 downto 0=”11111101”, B(7 downto 0)=”00000011”. From this case( clk=0 ), the inputs will not be loaded, so there is no calculation and no output. End1 equals to 0, which means no calculation.
Figure 5.6Waveform of Case Four
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6. TIMING ANALYSIS
The circuit is shown in Figure 6.1, where 2B is the barrel left shifter, -2B and –B are the 8 bit inverter, Booth Adder is an 8 bit Cripple Carry Adder.
Critical Path: RB2B-2BMUXBooth AdderBooth AdderBooth AdderBooth AdderRZ
Assume that the propagation delay of all the gates is the same.So one Full adder delay is . Delay of Mux 2:1 is . Delay of MUX 8:1 is . Delay of Barrel left shifter is Booth Adder’s delay is .Supposed the clock skew and jitter are omitted.
So,
The maximum frequency of operation:
Figure 6.1Sketch of Booth Multiplier Circuit
7. EXPANSION OF THE PROJECT
The method to design 8-by-8 bit Booth Multiplier can be expanded to build multiplier with more bits. The following is the expansion for 16-by-16 bit multiplier.
7.1 Register Expansion
The registers could increase from the both 8 bit D Flip-Flop to 16 bit D Flip-Flop and the output 16 bit D Flip-Flop to 32 D Flip-Flop.
7.2Multiplier Expansion
- Expansion of the top-level entity multiplier: Adding more four Partial_Product blocks.
- Expansion of the block Partial_Product: Changing all STD_VECTOR for 16 bits, extending the barrel shifter for 16 bits, keeping the other components same.
- Expansion of Booth_Adder: Changing to 16 bit Cripple Carry adder, for minimizing time delay, here the Cripple Selection Adder is a choice.
8. CONCLUSION
An 8-bit by 8-bit multiplier with booth algorithm is designed, analyzed. And it has beenverified by four general cases. The timing of the circuit and its expansion for more bits are discussed as well.
Using the booth algorithm to realize the 8-bit by 8-bit multiplier, it is obvious that it can save time against ordinary 8-bit by 8-bit multiplier. Meanwhile, the number of the components such as the full adder is also reduced in booth algorithm block. That means the area and power is saved.
It is easy to expand this multiplier into high order such as 16-bit by 16-bit multiplier. From the same main principle and structure, the 32-bit by 32-bit multiplier can be designed.
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APPENDIX A: BOOTH MULTIPLIER VHDLCODE
-- AND_2
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY AND_2 IS
PORT
(
A,B : INSTD_LOGIC;
Z : OUTSTD_LOGIC
);
END AND_2;
ARCHITECTURE RTL OF AND_2 IS
BEGIN
Z <= A and B;
END RTL;
-- OR_2
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY OR_2 IS
PORT
(
A,B : INSTD_LOGIC;
Z: OUTSTD_LOGIC
);
END OR_2;
ARCHITECTURE RTL OF OR_2 IS
BEGIN
Z <= A or B;
END RTL;
-- INVERTER
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY INVERT IS
PORT
(
A : INSTD_LOGIC;
Z: OUTSTD_LOGIC
);
END INVERT;
ARCHITECTURE RTL OF INVERT IS
BEGIN
Z <= not A;
END RTL;
-- INVERT_8
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity INVERT_8 is
port(
X : in STD_LOGIC_VECTOR(7 downto 0);
Xbar : out STD_LOGIC_VECTOR(7 downto 0)
);
end INVERT_8;
architecture RTL of INVERT_8 is
component INVERT
PORT
(
A : INSTD_LOGIC;
Z: OUTSTD_LOGIC
);
END component;
begin
invert0: INVERT PORT MAP(X(0),Xbar(0));
invert1: INVERT PORT MAP(X(1),Xbar(1));
invert2: INVERT PORT MAP(X(2),Xbar(2));
invert3: INVERT PORT MAP(X(3),Xbar(3));
invert4: INVERT PORT MAP(X(4),Xbar(4));
invert5: INVERT PORT MAP(X(5),Xbar(5));
invert6: INVERT PORT MAP(X(6),Xbar(6));
invert7: INVERT PORT MAP(X(7),Xbar(7));
end RTL;
- XOR_2
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY XOR_2 IS
PORT
(
A,B : INSTD_LOGIC;
Z: OUTSTD_LOGIC
);
END XOR_2;
ARCHITECTURE RTL OF XOR_2 IS
COMPONENT INVERT
PORT
(
A : INSTD_LOGIC;
Z: OUTSTD_LOGIC
);
END COMPONENT;
COMPONENT AND_2
PORT
(
A,B : INSTD_LOGIC;
Z: OUTSTD_LOGIC
);
END COMPONENT;
COMPONENT OR_2
PORT
(
A,B : INSTD_LOGIC;
Z: OUTSTD_LOGIC
);
END COMPONENT;
SIGNAL A1, B1, S1, S2: STD_LOGIC;
BEGIN
inverter1: INVERT PORT MAP(A, A1);
inverter2: INVERT PORT MAP(B, B1);
AA1: AND_2 PORT MAP(A, B1,S1);
AA2: AND_2 PORT MAP(A1,B,S2);
OR2: OR_2 PORT MAP(S1,S2,Z);
END RTL;
-- HALF ADDER
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY H_ADDER IS
PORT
(
A,B : INSTD_LOGIC;
SUM, CRY : OUTSTD_LOGIC
);
END H_ADDER;
ARCHITECTURE RTL OF H_ADDER IS
COMPONENT XOR_2
PORT
(
A,B : INSTD_LOGIC;
Z: OUTSTD_LOGIC
);
END COMPONENT;
COMPONENT AND_2
PORT
(
A,B : INSTD_LOGIC;
Z: OUTSTD_LOGIC
);
END COMPONENT;
BEGIN
X1: XOR_2 PORT MAP(A,B,SUM);
A1: AND_2 PORT MAP(A,B,CRY);
END RTL;
--FULL ADDER
library IEEE;
use IEEE.std_logic_1164.all;
entity Full_Adder IS
port( X : in std_logic;
Y : in std_logic;
Cin : in std_logic;
Z : out std_logic;
Cout: out std_logic);
end entity Full_Adder;
ARCHITECTURE RTL OF Full_Adder IS
COMPONENT H_ADDER
PORT
(
A,B : INSTD_LOGIC;
SUM, CRY : OUTSTD_LOGIC
);
END COMPONENT;
COMPONENT OR_2
PORT
(
A,B : INSTD_LOGIC;
Z: OUTSTD_LOGIC
);
END COMPONENT;
SIGNAL SUM1,CRY1,CRY2: STD_LOGIC;
begin
HA1: H_ADDER PORT MAP(X,Y,SUM1,CRY1);
HA2: H_ADDER PORT MAP(SUM1,Cin,Z,CRY2);
O_2: OR_2 PORT MAP(CRY1,CRY2,Cout);
end RTL;
-- MUX
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity MUX is
port(
A : in STD_LOGIC;
B : in STD_LOGIC;
SEL : in STD_LOGIC;
Z : out STD_LOGIC
);
end MUX;
architecture RTL of MUX is
COMPONENT INVERT
PORT
(
A : INSTD_LOGIC;
Z: OUTSTD_LOGIC
);
END COMPONENT;
COMPONENT AND_2
PORT
(
A,B : INSTD_LOGIC;
Z: OUTSTD_LOGIC
);
END COMPONENT;
COMPONENT OR_2
PORT
(
A,B : INSTD_LOGIC;
Z: OUTSTD_LOGIC
);
END COMPONENT;
SIGNAL SEL_BAR, S1, S2: STD_LOGIC;
begin
invert_1: INVERT PORT MAP(SEL, SEL_BAR);
A1: AND_2 PORT MAP(B,SEL_BAR,S2);
A2: AND_2 PORT MAP(A,SEL,S1);
OR2: OR_2 PORT MAP(S1,S2,Z);
end RTL;
-- MUX 8:1
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity MUX8_1 is
port(
A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC;
E : in STD_LOGIC;
F : in STD_LOGIC;
G : in STD_LOGIC;
H : in STD_LOGIC;
S0 : in STD_LOGIC;
S1 : in STD_LOGIC;
S2 : in STD_LOGIC;
Z : out STD_LOGIC
);
end MUX8_1;
architecture RTL of MUX8_1 is
component MUX
port(
A : in STD_LOGIC;
B : in STD_LOGIC;
SEL : in STD_LOGIC;
Z : out STD_LOGIC
);
end component;
signal TEMP: STD_LOGIC_VECTOR (5 downto 0);
begin
MUX0: MUX PORT MAP(B,A,S0,TEMP(0));
MUX1: MUX PORT MAP(D,C,S0,TEMP(1));
MUX2: MUX PORT MAP(F,E,S0,TEMP(2));
MUX3: MUX PORT MAP(H,G,S0,TEMP(3));
MUX4: MUX PORT MAP(TEMP(1),TEMP(0),S1,TEMP(4));
MUX5: MUX PORT MAP(TEMP(3),TEMP(2),S1,TEMP(5));
MUX6: MUX PORT MAP(TEMP(5),TEMP(4),S2,Z);
end RTL;
-- MUX_VECTOR 8:1
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity MUXVECTOR8_1 is
port(
S0 : in STD_LOGIC;
S1 : in STD_LOGIC;
S2 : in STD_LOGIC;
A : in STD_LOGIC_VECTOR(7 downto 0);
B : in STD_LOGIC_VECTOR(7 downto 0);
C : in STD_LOGIC_VECTOR(7 downto 0);
D : in STD_LOGIC_VECTOR(7 downto 0);
E : in STD_LOGIC_VECTOR(7 downto 0);
F : in STD_LOGIC_VECTOR(7 downto 0);
G : in STD_LOGIC_VECTOR(7 downto 0);
H : in STD_LOGIC_VECTOR(7 downto 0);
Z : out STD_LOGIC_VECTOR(7 downto 0)
);
end MUXVECTOR8_1;
architecture RTL of MUXVECTOR8_1 is
component MUX8_1
port(
A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC;
E : in STD_LOGIC;
F : in STD_LOGIC;
G : in STD_LOGIC;
H : in STD_LOGIC;
S0 : in STD_LOGIC;
S1 : in STD_LOGIC;
S2 : in STD_LOGIC;
Z : out STD_LOGIC
);
end component;
begin
MUX81_0: MUX8_1 PORT MAP(A(0),B(0),C(0),D(0),E(0),F(0),G(0),H(0),S0,S1,S2,Z(0));
MUX81_1: MUX8_1 PORT MAP(A(1),B(1),C(1),D(1),E(1),F(1),G(1),H(1),S0,S1,S2,Z(1));
MUX81_2: MUX8_1 PORT MAP(A(2),B(2),C(2),D(2),E(2),F(2),G(2),H(2),S0,S1,S2,Z(2));
MUX81_3: MUX8_1 PORT MAP(A(3),B(3),C(3),D(3),E(3),F(3),G(3),H(3),S0,S1,S2,Z(3));
MUX81_4: MUX8_1 PORT MAP(A(4),B(4),C(4),D(4),E(4),F(4),G(4),H(4),S0,S1,S2,Z(4));
MUX81_5: MUX8_1 PORT MAP(A(5),B(5),C(5),D(5),E(5),F(5),G(5),H(5),S0,S1,S2,Z(5));
MUX81_6: MUX8_1 PORT MAP(A(6),B(6),C(6),D(6),E(6),F(6),G(6),H(6),S0,S1,S2,Z(6));
MUX81_7: MUX8_1 PORT MAP(A(7),B(7),C(7),D(7),E(7),F(7),G(7),H(7),S0,S1,S2,Z(7));
end RTL;
-- BARREL SHIFTER LEFT ONE BIT
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity BSHIFTER_1 is
port(
S0 : in STD_LOGIC;
X : in STD_LOGIC_VECTOR(7 downto 0);
Y : out STD_LOGIC_VECTOR(7 downto 0)
);
end BSHIFTER_1;
architecture RTL of BSHIFTER_1 is
component MUX
port(
A : in STD_LOGIC;
B : in STD_LOGIC;
SEL : in STD_LOGIC;
Z : out STD_LOGIC
);
end component;
signal init: STD_LOGIC;
begin
init<='0';
MUX0 : MUX PORT MAP( init,X(0),S0,Y(0));
MUX1 : MUX PORT MAP(X(0),X(1),S0,Y(1));
MUX2 : MUX PORT MAP(X(1),X(2),S0,Y(2));
MUX3 : MUX PORT MAP(X(2),X(3),S0,Y(3));
MUX4 : MUX PORT MAP(X(3),X(4),S0,Y(4));
MUX5 : MUX PORT MAP(X(4),X(5),S0,Y(5));
MUX6 : MUX PORT MAP(X(5),X(6),S0,Y(6));
MUX7 : MUX PORT MAP(X(6),X(7),S0,Y(7));
end RTL;
--1-BIT D-FLIP FLOP
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity D_FF is
port(
d,cp,load,clr:in STD_LOGIC;
q:out STD_LOGIC);
end D_FF;
architecture content of D_FF is
begin
process(cp)
begin
if(cp='1' and cp'event and load='1')
then if clr='0' then q<=d ;
else q<='0';
end if;
end if;
end process;
end content;
--8-BIT D-FLIP FLOP
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity DFF_8 is
port(
load,clr,cp:in STD_LOGIC;
d: in STD_LOGIC_VECTOR(7 downto 0);
q: out STD_LOGIC_VECTOR(7 downto 0));
end DFF_8;
architecture RTL of DFF_8 is
component D_FF
port(
d,cp,load,clr:in STD_LOGIC;
q:out STD_LOGIC);
end component;
begin
DFF0:D_FF port map(d(0),cp,load,clr,q(0));
DFF1:D_FF port map(d(1),cp,load,clr,q(1));
DFF2:D_FF port map(d(2),cp,load,clr,q(2));
DFF3:D_FF port map(d(3),cp,load,clr,q(3));
DFF4:D_FF port map(d(4),cp,load,clr,q(4));
DFF5:D_FF port map(d(5),cp,load,clr,q(5));
DFF6:D_FF port map(d(6),cp,load,clr,q(6));
DFF7:D_FF port map(d(7),cp,load,clr,q(7));
end RTL;
--16-BIT D-FLIP FLOP
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity DFF_16 is
port(
cp,clr:in STD_LOGIC;
d: in STD_LOGIC_VECTOR(15 downto 0);
q: out STD_LOGIC_VECTOR(15 downto 0));
end DFF_16;
architecture RTL of DFF_16 is
component D_FF is
port(
d,cp,load,clr:in STD_LOGIC;
q:out STD_LOGIC);
end component;
signal load:STD_LOGIC;
begin
load<='1';
DFF0:D_FF port map(d(0),cp,load,clr,q(0));
DFF1:D_FF port map(d(1),cp,load,clr,q(1));
DFF2:D_FF port map(d(2),cp,load,clr,q(2));
DFF3:D_FF port map(d(3),cp,load,clr,q(3));
DFF4:D_FF port map(d(4),cp,load,clr,q(4));
DFF5:D_FF port map(d(5),cp,load,clr,q(5));
DFF6:D_FF port map(d(6),cp,load,clr,q(6));
DFF7:D_FF port map(d(7),cp,load,clr,q(7));
DFF8:D_FF port map(d(8),cp,load,clr,q(8));
DFF9:D_FF port map(d(9),cp,load,clr,q(9));
DFF10:D_FF port map(d(10),cp,load,clr,q(10));
DFF11:D_FF port map(d(11),cp,load,clr,q(11));
DFF12:D_FF port map(d(12),cp,load,clr,q(12));
DFF13:D_FF port map(d(13),cp,load,clr,q(13));
DFF14:D_FF port map(d(14),cp,load,clr,q(14));
DFF15:D_FF port map(d(15),cp,load,clr,q(15));
end RTL;
--BOOTH ADDER
library IEEE;
use IEEE.std_logic_1164.all;
entity Booth_Adder is
port(X: in std_logic_vector(7 downto 0);
Y: in std_logic_vector(7 downto 0);
Cin: in std_logic;
Z: out std_logic_vector(7 downto 0);
Cout: out std_logic);
end Booth_Adder;
architecture RTL of Booth_Adder is
component Full_Adder is
port(X:in std_logic;
Y: in std_logic;
Cin:in std_logic;
Z:out std_logic;
Cout: out std_logic);
end component;
signal s: std_logic_vector(7 downto 0);
begin
FA0: Full_Adder port map(X(0),Y(0),Cin,Z(0),s(0));
FA1: Full_Adder port map(X(1),Y(1),s(0),Z(1),s(1));
FA2: Full_Adder port map(X(2),Y(2),s(1),Z(2),s(2));
FA3: Full_Adder port map(X(3),Y(3),s(2),Z(3),s(3));
FA4: Full_Adder port map(X(4),Y(4),s(3),Z(4),s(4));
FA5: Full_Adder port map(X(5),Y(5),s(4),Z(5),s(5));
FA6: Full_Adder port map(X(6),Y(6),s(5),Z(6),s(6));
FA7: Full_Adder port map(X(7),Y(7),s(6),Z(7),s(7));
Cout<=s(7);
end RTL;
--PARTIAL PRODUCT
library IEEE;
use IEEE.std_logic_1164.all;
entity Partial_Product is
port (X : in std_logic_vector(2 downto 0);
Y : in std_logic_vector(7 downto 0);
Sin : in std_logic_vector(7 downto 0);
Sout : out std_logic_vector(7 downto 0);
prod : out std_logic_vector(1 downto 0));
end entity Partial_Product;
architecture RTL of Partial_Product is
component Full_Adder is
port( X : in std_logic;
Y : in std_logic;
Cin : in std_logic;
Z : out std_logic;
Cout : out std_logic);
end component;
component Booth_Adder is
port(X: in std_logic_vector(7 downto 0);
Y: in std_logic_vector(7 downto 0);
Cin: in std_logic;
Z: out std_logic_vector(7 downto 0);
Cout: out std_logic);
end component;
component BSHIFTER_1
port(
S0 : in STD_LOGIC;
X : in STD_LOGIC_VECTOR(7 downto 0);
Y : out STD_LOGIC_VECTOR(7 downto 0)
);
end component;
component INVERT_8
port(
X : in STD_LOGIC_VECTOR(7 downto 0);
Xbar : out STD_LOGIC_VECTOR(7 downto 0)
);
end component;
component MUX8_1
port(
A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC;
E : in STD_LOGIC;
F : in STD_LOGIC;
G : in STD_LOGIC;
H : in STD_LOGIC;
S0 : in STD_LOGIC;
S1 : in STD_LOGIC;
S2 : in STD_LOGIC;
Z : out STD_LOGIC
);
end component;
component MUXVECTOR8_1
port(
S0 : in STD_LOGIC;
S1 : in STD_LOGIC;
S2 : in STD_LOGIC;
A : in STD_LOGIC_VECTOR(7 downto 0);
B : in STD_LOGIC_VECTOR(7 downto 0);
C : in STD_LOGIC_VECTOR(7 downto 0);
D : in STD_LOGIC_VECTOR(7 downto 0);
E : in STD_LOGIC_VECTOR(7 downto 0);
F : in STD_LOGIC_VECTOR(7 downto 0);
G : in STD_LOGIC_VECTOR(7 downto 0);
H : in STD_LOGIC_VECTOR(7 downto 0);
Z : out STD_LOGIC_VECTOR(7 downto 0)
);
end component;
signal Y_out : std_logic_vector(7 downto 0);
signal Partial_sum: std_logic_vector(7 downto 0);
signal Ybar : std_logic_vector(7 downto 0);
signal twoY : std_logic_vector(7 downto 0);
signal twoYbar : std_logic_vector(7 downto 0);
signal Y_INIT : std_logic_vector(7 downto 0):= x"00";
signal cout : std_logic;
signal cin : std_logic;
signal MSBin : std_logic;
signal MSBout : std_logic;
signal temp : std_logic;
signal shifter_1 : std_logic;
begin
shifter_1<='1';
Two_Y: BSHIFTER_1 PORT MAP(shifter_1,Y,twoY);
Y_BAR: INVERT_8 PORT MAP (Y,Ybar);
Two_YBAR: INVERT_8 PORT MAP (twoY,twoYbar);
BOOTHCODER_OUT: MUXVECTOR8_1 PORT MAP(X(2),X(1),X(0),Y_INIT,twoYbar,Y,Ybar,Y,Ybar,twoY,Y_INIT,Y_out);
C_IN: MUX8_1 PORT MAP('0','1','0','1','0','1','0','0',X(2),X(1),X(0),cin);
MSB_IN: MUX8_1 PORT MAP('0',Ybar(7),Y(7),Ybar(7),Y(7),Ybar(7),Y(7),'0',X(2),X(1),X(0),MSBin);
a1: Booth_Adder port map(Sin, Y_out, cin, Partial_sum, cout);
a2: Full_Adder port map(Sin(7), MSBin , cout, MSBout, temp);
Sout(5 downto 0) <= Partial_sum(7 downto 2);
Sout(7) <= MSBout;
Sout(6) <= MSBout;
prod <= Partial_sum(1 downto 0);
end RTL;
--BOOTH MULTIPLIER TOP LEVEL
library IEEE;
use IEEE.std_logic_1164.all;
entity Multiplier is
port (
load,clr,clk: in STD_LOGIC;
a : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 downto 0);
z : out std_logic_vector(15 downto 0);
end1: out STD_LOGIC);
end Multiplier;
architecture behavioral of Multiplier is
component DFF_8
port(
load,clr,cp:in STD_LOGIC;
d: in STD_LOGIC_VECTOR(7 downto 0);
q: out STD_LOGIC_VECTOR(7 downto 0));
end component;
component DFF_16
port(
cp,clr:in STD_LOGIC;
d: in STD_LOGIC_VECTOR(15 downto 0);
q: out STD_LOGIC_VECTOR(15 downto 0));
end component;
component Partial_Product
port(
X : in std_logic_vector(2 downto 0);
Y : in std_logic_vector(7 downto 0);
Sin : in std_logic_vector(7 downto 0);
Sout : out std_logic_vector(7 downto 0);
prod : out std_logic_vector(1 downto 0));
end component;
signal a_in :STD_LOGIC_VECTOR(7 downto 0);
signal b_in :STD_LOGIC_VECTOR(7 downto 0);
signal s_buffer:std_logic_vector(15 downto 0);
signal end2 :STD_LOGIC;
signal init : std_logic_vector(7 downto 0) := x"00";
signal initial_sum: std_logic_vector(2 downto 0);