Introduction to Embedded Microcomputer Systems Lecture 15.12
A device driver is a collection of software functions that allow higher level software to utilize an I/O device.
Collection of public methods (subroutines)
ADC_Init
ADC_In
Collection of private objects (subroutines, globals, I/O ports)
ATDCTL2
ATDCTL5
ATDDR0
complexity abstraction
divide a complex problem into simple subcomponents
functional abstraction
divide a problem into modules
grouped by function
*****************tut3****************************
ATDCTL2=0x80; set bit 7 to enable ADC
ATDCTL3=0x08; sequence length=1
ATDCTL4=0x01; 10-bit, divide by 2
ATDCTL5 write channel number to start ADC
· channel number $80 to $87
ATDSTAT bit 7 SCF
· cleared by write to ATDCTL5
· set when ADC finished
ATDDR0 first 10-bit ADC result
· precision 10-bit, 1024 alternatives
· range 0 to +5V
· resolution (5-0)/1024 = 5 mV
Digital Output = 1024*Vin/5
Analog Input (V) / Digital Output0.000 / %0000000000 $000 0
0.005 / %0000000001 $001 1
2.500 / %1000000000 $200 512
3.750 / %1100000000 $300 192
5.000 / %1111111111 $3FF 1023
Table 5.11. Straight binary format used.
1) run tut3
2) see ADC device driver
3) show ADC_Init
Turns it on
Sets it to 10-bit mode
4) show ADC_In
write channel number to ATDCTL5
wait for SCF flag in ATDSTAT
read 10-bit result from ATDDR0
5) show SCI_OutDec
Lab 7 (same data flow as tut3)
Slow moving temperature wave.
Run solution to Lab 7, show how to prove real time DAS
start ADC at a regular rate
measure the jitter
1ms-dt < tn – tn-1 < 1ms+dt
Lab 7 (same data flow as tut3)
Lab 7,
Sample ADC every 0.5s
Map (0 to 1023) into (0000 to +4000)
Position = 4000*(Sample)/1024
Position = 125*(Sample)/32
Fixed-Point output
1234 is displayed a “1.234 cm”
11.10.2. 6812 ADC System
Most of the 6812 microcontrollers have built in ADC converters. This section will specifically cover the MC9S12C32, but the other 6812 devices operate in a very similar manner. The I/O registers used for the ADC are listed in Table 11.13. The ADC on the MC9S12C32 can be operated in 8-bit mode or 10-bit mode. The 8 pins of Port AD can be individually defined to be analog input, digital output, or digital input. We set the corresponding bit in the ATDDIEN register to be 1 for digital or 0 for analog input. If a pin is digital, then the corresponding bit in the DDRAD register specifies input(0) or output(1). The ADC digital output can be right- or left-justified within the 16bit result register, and it can be in a signed or unsigned format. When the ADC is triggered, it performs a sequence of conversions, with the sequence length being any number from 1 to 8 conversions. When performing a sequence, it can convert the same channel multiple times or it can convert different channels during the sequence. We can trigger ADC conversions in three ways. The first way is to use an explicit software trigger (write to ATDCTL5), and when the conversions are complete, the SCF flag is set. The examples in Programs 11.12 and 11.13 employ the explicit software trigger to start an ADC conversion. The second way trigger the ADC is continuous mode. In this mode, the ADC sequence is repeated over and over continuously. The third way is to connect an external trigger to the digital input on PAD7. With an external trigger we can use busy-wait synchronization (gadfly) on the SCF flag, or arm interrupts (ASCIE=1) on the ASCIF flag. The results of the ADC conversions can be found in the ATDDR0 to ATDDR7 result registers, where the register number refers to the sequence number. In other words, ATDDR0 contains the result of the first conversion in the sequence, ATDDR1 contains the result of the second conversion,… and ATDDR7 contains the result of the eighth conversion.
Address / Bit 7 / 6 / 5 / 4 / 3 / 2 / 1 / Bit 0 / Name$0082 / ADPU / AFFC / AWAI / ETRIGLE / ETRIGP / ETRIG / ASCIE / ASCIF / ATDCTL2
$0083 / 0 / S8C / S4C / S2C / S1C / FIFO / FRZ1 / FRZ0 / ATDCTL3
$0084 / SRES8 / SMP1 / SMP0 / PRS4 / PRS3 / PRS2 / PRS1 / PRS0 / ATDCTL4
$0085 / DJM / DSGN / SCAN / MULT / 0 / CC / CB / CA / ATDCTL5
$0086 / SCF / 0 / ETORF / FIFOR / 0 / CC2 / CC1 / CC0 / ATDSTAT0
$008B / CCF7 / CCF6 / CCF5 / CCF4 / CCF3 / CCF2 / CCF1 / CCF0 / ATDSTAT1
$008D / Bit 7 / 6 / 5 / 4 / 3 / 2 / 1 / Bit 0 / ATDDIEN
$0270 / PTAD7 / PTAD6 / PTAD5 / PTAD4 / PTAD3 / PTAD2 / PTAD1 / PTAD0 / PTAD
$0272 / DDRAD7 / DDRAD6 / DDRAD5 / DDRAD4 / DDRAD3 / DDRAD2 / DDRAD1 / DDRAD0 / DDRAD
address / msb / lsb / Name
$0090 / 15 / 14 / 13 / 12 / 11 / 10 / 9 / 8 / 7 / 6 / 5 / 4 / 3 / 2 / 1 / 0 / ATDDR0
$0092 / 15 / 14 / 13 / 12 / 11 / 10 / 9 / 8 / 7 / 6 / 5 / 4 / 3 / 2 / 1 / 0 / ATDDR1
$0094 / 15 / 14 / 13 / 12 / 11 / 10 / 9 / 8 / 7 / 6 / 5 / 4 / 3 / 2 / 1 / 0 / ATDDR2
$0096 / 15 / 14 / 13 / 12 / 11 / 10 / 9 / 8 / 7 / 6 / 5 / 4 / 3 / 2 / 1 / 0 / ATDDR3
$0098 / 15 / 14 / 13 / 12 / 11 / 10 / 9 / 8 / 7 / 6 / 5 / 4 / 3 / 2 / 1 / 0 / ATDDR4
$009A / 15 / 14 / 13 / 12 / 11 / 10 / 9 / 8 / 7 / 6 / 5 / 4 / 3 / 2 / 1 / 0 / ATDDR5
$009C / 15 / 14 / 13 / 12 / 11 / 10 / 9 / 8 / 7 / 6 / 5 / 4 / 3 / 2 / 1 / 0 / ATDDR6
$009E / 15 / 14 / 13 / 12 / 11 / 10 / 9 / 8 / 7 / 6 / 5 / 4 / 3 / 2 / 1 / 0 / ATDDR7
Table 11.13. MC9S12C32 registers used for analog to digital conversion.
The ATDCTL2 contains bits that activate the ADC module. The 6812 ADC system is enabled by setting ADPU equal to 1. The ADC will request an interrupt on the completion of a conversion sequence if the arm bit ASCIE is set. ASCIF is the ATD Sequence Complete Interrupt Flag. If ASCIE=1 the ASCIF flag equals the SCF flag, else ASCIF reads zero. Write operations to ATDCTL2 have no effect on ASCIF. ETRIGE is the External Trigger Mode Enable bit. This bit enables an external trigger using the digital input from Port AD bit 7. The external trigger allows us to synchronize sample and ATD conversions processes with external events. If external triggering is enabled, then the type of trigger is defined in the ETRIGLE and ETRIGP bits as specified in Table 11.14.
ETRIGLE / ETRIGP / External Trigger mode0 / 0 / Falling edge of PAD7 starts a conversion sequence
0 / 1 / Rising edge of PAD7 starts a conversion sequence
1 / 0 / Perform ADC conversions when PAD7 is low
1 / 1 / Perform ADC conversions when PAD7 is high
Table 11.14. External trigger modes for the MC9S12C32 ADC.
The ATDCTL3 and ATDCTL4 contain bits that specify the ADC mode. S8C, S4C, S2C, S1C control the number of conversions per sequence. Let n be the four-bit number specified by these bits. For values of n from 1 to 7, n specifies the sequence length. For values of n equal to 0 or 8-15, the sequence length is 8. At reset, the default sequence length is 4 (0100), maintaining software continuity to HC12 family. This book will not discuss FIFO mode or freeze mode. SRES8 is the ADC Resolution Select bit. This bit selects the resolution of ADC conversion as either 8 (SRES8=1) or 10 bits (SRES8=0). The ADC converter has an accuracy of 10 bits; however, if low resolution is acceptable, selecting 8-bit resolution will reduce the conversion time.
The time to perform an ADC conversion is determined by the E clock and the ATDCTL4 register. The ATDCTL4 register selects the sample period and PRS-Clock prescaler. SMP1, SMP0 are the Sample Time Select bits. These two bits select the length of the second phase of the sample time in units of ATD conversion clock periods, as listed in Table 11.15. The sample time consists of two phases. The first phase is two ATD conversion clock periods long and transfers the sample quickly (via the buffer amplifier) onto the ADC machine’s storage node. The second phase attaches the external analog signal directly to the storage node for final charging and high accuracy. Table 11.15 lists the lengths available for the second sample phase. Let m be the 5-bit number formed by bits PRS4-0. Let fE be the frequency of the E clock. The ATD conversion clock frequency is calculated as follows:
ATD clock frequency = ½ fE /(m+1)
The default (after reset) prescaler value is 5, which results in a default ATD conversion clock frequency that is the E clock divided by 12. The choice of these parameters involves a tradeoff between accuracy and speed. Freescale recommends the ADC clock frequency be restricted to the 500 kHz to 2 MHz range. For analog signals with the white noise, we can essentially add an analog low pass filter by increasing the ADC sample time. To increase conversion speed, we wish to select a fast clock and short sample period. The last factor to consider is the slewing rate of the input signal. For signals with a high slope, dV/dt, we need to select a faster conversion time (i.e., shorter sample time). More discussion about slewing rate will be made in the next chapter when considering the need for a sample and hold analog latch. For a 24 MHz E clock, the possible m prescales range from 5 (ADCclock=2 MHz) to 23 (ADCclock=500 kHz). Other choices are not recommended.
SMP1 / SMP0 / First Sample Phase / Second Sample Phase / Total Sample Time0 / 0 / 2 ADC clock periods / 2 ADC clock periods / 4 ADC clock periods
0 / 1 / 2 ADC clock periods / 4 ADC clock periods / 6 ADC clock periods
1 / 0 / 2 ADC clock periods / 8 ADC clock periods / 10 ADC clock periods
1 / 1 / 2 ADC clock periods / 16 ADC clock periods / 18 ADC clock periods
Table 11.15. Sampling time for the 6812 ADC .
Writing to ATDCTL5 register will start an ADC conversion. To begin continuous conversions, we write to the ATDCTL5 with SCAN=1. On the other hand, if we write to ATDCTL5 with SCAN=0, only one sequence occurs. CC, CB, CA select the analog input channel(s) whose signals are sampled and converted to digital codes. Because the result registers (16 bits) are wider than the ADC digital code (8 or 10 bits), we must choose where in the result register to put the digital code. DJM is the Result Register Data Justification bit, where 1 means right-justified and 0 means left-justified data in the result registers. DSGN selects between signed and unsigned format. We set DSGN to 1 for signed data representation and we set it to 0 for unsigned data representation. Table 11.16 describes the four possible 10-bit data formations for the MC9S12C32. When MULT is 0, the ATD sequence controller samples only from the specified analog input channel for an entire conversion sequence. When MULT is 1, the ATD sequence controller samples across channels. The number of channels sampled is determined by the sequence length value (S8C, S4C, S2C, S1C). The first analog channel examined is determined by channel selection code (CC, CB, CA control bits); subsequent channels sampled in the sequence are determined by incrementing the channel selection code.
The status register contains a status bit, SCF, which we use to poll for the ADC conversion completion. The SCF flag is cleared by writing data into the ADCTL5 (i.e., starting a new conversion.) The SCF flag can also be cleared by writing a 1 to it. The CC2,CC1,CC0 bits are the sequence counter as the ADC steps through a conversion sequence. The CCFn bits are individual flags for each of the conversions.
Performance Tip: If we are interested in a single conversion, we could start the ADC , wait for CCF0, then read the result in ATDDR0.
11.10.3. ADC Software
The MC9S12C32 subroutine, AD_In, will return a 10-bit value representing the analog input. Table 11.16 shows the 8-bit format available on the 6811 and the four 10-bit formats available on 6812. When the 6812 inserts an 8- or 10-bit data into the 16-bit result register it will pad the extra bits with 0s, but Table 11.16 is shown with bits 15-10 having been sign-extended from bit 9. The C code to perform this sign extension is
Result = ATDDR0; // 10-bit signed, right-justified
if(Result&0x200) Result = Result|0xF8; // sign extend if negative
Analog Input (V) / 8-bit unsignedDigital Output / 10-bit unsigned
Right-justified / 10-bit unsigned
Left-justified / 10-bit signed
Right-justified / 10-bit signed
Left-justified
0.000 / $00 0 / $0000 0 / $0000 0 / $FE00 -512 / $8000 -32768
0.005 / $00 0 / $0001 1 / $0040 64 / $FE01 -511 / $8040 -32704
0.020 / $01 1 / $0004 4 / $0100 256 / $FE04 -508 / $8100 -32512
2.500 / $80 128 / $0200 512 / $8000 32768 / $0000 0 / $0000 0
3.750 / $C0 192 / $0300 768 / $C000 49152 / $0100 256 / $4000 16384
5.000 / $FF 255 / $03FF 1023 / $FFC0 65472 / $01FF 511 / $7FC0 32704
Table 11.16 Binary formats used by the Freescale internal ADCs.