7.2.2. The Tuned Cascode Amplifier
A cascode circuit loaded with a parallel resonance circuit is shown in Fig. 7.16. M1 and M2 are biased in the saturation region with VG1 and VG2. The load of M1 is the input impedance of M2, operating as a common gate circuit.
We know that
Figure 7.13. (a) Schematic diagram of a tuned common source amplifier. (b) The small-signal equivalent circuit. C represent the total capacitance ( the sum of the external capacitor C’, the output capacitance of the transistor, the input capacitance of the following stage and the parasitics). Reff is the parallel equivalent of the output resistance of the transistor, the input resistance of the following stage and the parallel resistance corresponding the losses of the resonance circuit.
(5.2)
where Yo represents the total output load admittance, that is the parallel equivalent of C, L and Reff for our circuit[1]:
(7.28)
To derive the variations of the magnitude and the phase of the gain with frequency, it is possible to write (7.28) in the frequency domain, or to use the pole-zero diagram of the gain function. We’ll prefer the second way:
(7.28) can be arranged in terms of its poles and zero as
(7.29)
where (7.30)
and with
and
(7.30-a)
The pole-zero diagram of the gain function is given in Fig. 7.14-a. For any ω value the magnitude and phase of the gain can be obtained as
(7.31)
(7.32)
Figure 7.14. (a) The pole-zero diagram of the gain function of a tuned amplifier,
(b) its simplified form for the vicinity of the resonance frequency (note that (s-sp1) is
drawn for the upper 3 dB frequency of the gain).
Provided that and , that are valid for most practical cases, for the vicinity ω0 the magnitude and phase can be approximated as
(7.31-a)
(7.32-a)
The simplified form of the pole-zero diagram of the amplifier corresponding to (7.31-a) and (7.32-a), valid for and around of the resonance frequency is shown in Fig. 7.14-b. From this figure the 3 dB frequencies and the band-width of the amplifier can be found as
(7.33)
that are same as of a parallel resonance circuit.
The magnitude of the gain corresponding to the resonance frequency can be calculated from (7.31-a) with
(7.34)
and similarly the phase angle for ω0
(7.35)
Along the calculations above we assumed that the zero of the voltage gain related to the drain-gate capacitance is far away on the right half-plane and therefore negligible. This assumption corresponds to , that is usually valid. Under this assumption the voltage gain (2.28) can be written as
(7.36)
where Z0 is the effective impedance of the parallel resonance circuit.
------
Example 7.2.
Check the validity of the assumption of for a ST 0.13 micron NMOS transistor operating in the velocity saturation regime. The operating frequency of the amplifier is 3 GHz.
Under the velocity saturation, (that is the case for a 0.13 micron transistor as shown in Part-1) the transconductance is and the drain-gate capacitance Cdg = W×CDGW. Therefore
that is independent of the gate width. The related parameter values for the ST 0.13 micron technology are tox=2.3×10-9 [m] (that correspond to Cox = 15×10-3 f/m2), and CDGW=5.18×10-10 [f/m]. The saturation velocity of electrons in the channel was given in Part-1 as 6.5×104 [m/s]. Therefore
that corresponds to an error of 1% on the magnitude of the gain and an excess phase shift of only 0.57º.
------
Problem 7.4.
An amplifier tuned to 1GHz is designed with a AMS 035 NMOS transistor with W=100 mm and L=0.35 mm. The drain current is 5 mA. Calculate the gain and phase errors of this amplifier if the effects of Cdg are neglected.
------
The numerical results of this example show that the effects of the drain-gate capacitance is negligibly small. Then why this capacitance is known (famous) with its adverse effects on tuned amplifiers? The answer is related to the effects of Cgs on the input admittance of the amplifier.
The input admittance of a common source amplifier was found as
(5.3-a)
The first term is apparently capacitive, but the second term (the Miller component) needs to be investigated. Let us to write the Miller admittance in frequency domain, and then calculate the real and imaginary parts:
(7.37)
(7.38)
From (7.38) it is possible to see that;
- At the resonance frequency (for ω = ω0 ) the input conductance is
that strongly depends on Cdg.
- Above the resonance frequency (where the load impedance is capacitive), the input conductance is positive and is a function of frequency.
- Below the resonance frequency (where the load impedance is inductive), the input conductance has a dominant negative component and changes with frequency.
This frequency dependent input conductance and especially its negativity below the ω0 resonance frequency of the output load is important from different points of view:
- In case of a non-ideal input signal source (that is the realistic case), the signal voltage on the gate of the transistor changes with frequency. Therefore the overall frequency characteristic is determined not only by the output load, but also by the internal impedance of the signal source.
- If a tuned circuit exists in parallel to the input, due to the positive parallel conductance above ω0 and the negative parallel conductance below ω0, the quality factor of this circuit decreases above ω0 and increases below ω0. The result is the skew of the frequency characteristic of the input resonance circuit, that affects the overall frequency characteristic of the circuit.
- The negative conductance component of the input admittance can over- compensate the losses of the input resonance circuit and can lead the circuit to oscillate.
According to (7.37) the imaginary part of the input admittance of a tuned amplifier is also depends on the frequency. This is not severe as the varying, even negative input conductance. It only acts on the tuning of the input resonance circuit, if there is any.
To exemplify these results the PSpice simulation results of a simple tuned amplifier are given in Fig. 7.15. Transistor is a AMS 035 NMOS transistor with L = 0.35 mm and W = 200 mm. D.C. supplies are VDD = 3 V and VG = 0.8 V. L =10 nH and C is trimmed to 2.34 pF to tune the circuit to f0 = 1 GHz. The parallel resistance representing the total losses of the resonance circuit is 1 k ohm, that corresponds to Q = 15.9.
Curve-A and B show the variations of the input capacitance and the input conductance, respectively. The negative input conductance below f0 and positive input conductance above f0 are obviously seen from curve-B. The maximum values of the input conductance are 1.2 mS and correspond approximately to the 3 dB frequencies of the gain that is plotted as curve-C.
These dramatic variations of the input admittance of a tuned MOS amplifier are obviously due o the drain-gate capacitance of the device, that is unavoidable and its adverse effects increase with frequency. Consequently a circuit as shown in Fig. 7. 13 can be used only at the lower end of the RF spectrum. For high frequency RF amplifiers, the extensively used solution is the “cascode” circuit that was investigated in general in Section 5.4.
Figure 7.15. Variations of the input capacitance (A), the input conductance (B) and the voltage gain of the amplifier (C). Note the fluctuations of the input capacitance and the input conductance, and especially negativity of the input conductance below the resonance frequency.
the input impedance of a common gate circuit is approximately equal to the parallel equivalent of 1/gm and Csg. Consequently the voltage gain of M1 is low and equal to up to the frequencies close to . Therefore the
Miller component of the input admittance of M1 is smaller compared to that of a high gain common source amplifier. In addition, since the output resistance of a cascode circuit is higher than the output resistance of a common source circuit, the effective Q of the load becomes higher.
Figure 7.16. Schematic diagram of a tuned cascode amplifier.
To visualize the benefits of the cascode configuration, the simulation results of a cascode amplifier is given in Fig. 7.17. The parameters of the circuit are same as the parameters of the common source amplifier, whose simulation results were given in Fig. 7.15:
M1 and M2: AMS 035 NMOS transistor. L = 0.35 mm, W = 200 mm.
D.C. supplies: VDD = 3 V and VG1 = 0.8 V, VG2 = 1.5 V
L = 10 nH, C’ = 2.34 pF (f0 = 1 GHz)
Parallel resistance representing the total losses of L and C is 1 k ohm.
To ease the comparison, the vertical axes in Fig. 7.17 are intentionally chosen as same as that of the Fig. 7.15. The obvious advantages of the cascode circuit can be summarized as follows:
- The input capacitance is almost constant in the whole frequency band and equal to the input capacitance of M1.
- The input conductance is positive and almost constant in the whole frequency band. These mean that the input of the circuit is a well defined load for the driving signal source and has no adverse effect if there is another tuned circuit parallel to the input.
- The band-width of the gain is smaller (the effective Q is higher) compared to that of the reference common source circuit. This is the result of the high output resistance of the common gate output transistor M2, as expected.
Figure 7.17. Variations of the input capacitance (A), the input conductance (B) and the voltage gain (C).of the tuned cascode amplifier. Note the almost constant input capacitance and the input conductance.
[1] It is obvious that for , the voltage gain can be written as . Consequently the frequency characteristic and the –3dB frequencies of the amplifier are same as of the total load impedance, Z0. Here a less straightforward approach will be used to enable to discuss the effects of the “zero” of the gain function and to prepare the reader to the concepts that will be used to investigate the stagerred tuning in Part 7-3.