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EX1 Section B: Logic functions and combinational circuits
EX 1 DIGITAL CIRCUITS AND SYSTEMS
Section B: Logic functions and combinational circuits
1.1 Cooperative group
TEAM NUMBER: ______
DUE DATE: ______1st review due date: ______
STUDY TIME:
Study time(in hours) / Group work / Classroom and laboratory sessions / Sessions out of classroom
Individual / Student 1
Student 2
Student 3
STATEMENT:
My signature below indicates that I have (1) made equitable contribution to EX 1 as a member of the group, (2) read and fully agree with the contents (i.e., results, conclusions, analyses, simulations) of this document, and (3) acknowledged by name anyone outside this group who assisted this learning team or any individual member in the completion of this document.
Today’s date: ______
Active members Roles: (reporter, simulator, etc.)
(1) ______
(2) ______
(3) ______
Acknowledgement of individual(s) who assisted this group in completing this document:
(1) ______
(2) ______
1.2 Abstract
Explain here the most significant developments, results or conclusions about the exercise. Use the remaining space in this sheet (200 words maximum).
(This section is mandatory. You must complete it in order to get a mark.)
CONTENT
Section B: Logic functions and combinational circuits 1
1.1 Cooperative group 1
1.2 Abstract 1
1.3 Description 3
1.4 Topics 3
1.5 Part 1: The basics (analysis) 4
1.5.1 Analysis of combinational circuit based on logic gates 4
1.5.2 WolframAlpha 4
1.5.3 Installing and using Proteus-ISIS 5
1.5.4 Installing and using ispLEVER Classic 5
1.6 Part 2: The basics (design process) 10
1.6.1 Truth table, sum of minterms and product of maxterms 10
1.6.2 Simplifying logic functions using Minilog 10
1.6.3 Circuits in CMOS technology 10
1.6.4 Circuits in LS-TTL technology 11
1.7 VHDL simulation using ModelSim or Active HDL 11
1.7.1 Flat design in VHDL 11
1.7.2 Hierarchical design in VHDL 11
1.8 Part 3: Building a library of standard combinational circuits 11
1.9 Another design example 12
1.10 Problem solution (títol 2) 13
1.10.1 Part 1 (títol 3) 13
1.11 References 13
1.12 Study plan to solve the exercise 13
1.13 Topics and activities checklist 14
1.14 Grading grid 15
1.15 Questions in solving EX1 15
1.3 Description
In this Section B of EX1, the basics of combinational circuits will be discussed. In Part 1 the process of analysing a given circuit until the specifications are determined. In Part 2 the design process is presented, from the initial specifications to the final circuit implementations. In Part 3, we will start the implementation of a variety of basic combinational building blocks using several of the techniques presented previously; the aim has to be the development of a library of components, which can be systematically enlarged in future terms.
The problem also introduces the installation and use of the latest computer aided design (CAD) software for analyse, design, simulate and synthesise combinational circuits into simple programmable logic devices (sPLD):
- WolframAlpha to deduce truth tables and equations from circuits or logic diagrams
- Minilog or Logic Friday (Espresso algorithm) to minimise logic equations
- ModelSim or ActiveHDL to simulate VHDL projects
- Proteus-ISIS, a complete virtual laboratory environment with includes SPLD models such as the GAL22V10
- ispLEVER Classic and ispVM System from Lattice Semiconductor and Synplify from Synplicity, to synthesise logic circuits into PLD.
Finally, you will have the opportunity to use word processors, spelling checkers, graphic tools and other auxiliary software in order to prepare documents which reflect the quality of your work.
1.4 Topics
The following topics have been listed from the course’s specific and cross-curricular learning objectives[1]: #1, #2, #3, #5, #6, #7. After studying Chapter 1 and successfully completing all the assignments in this task, you will be able to:
------Part 1------
1. Use and explain the functionality of logic gates AND, NAND, OR, NOR, XOR, NXOR, NOT)
2. Analyze a logic circuit built using logic gates. Analysis concept map.
3. Use the application WolframAlpha to verify logic equations and determine the truth table of a combinational circuit.
4. Use the HADES JAVA-based platform[2] to visualise and analyse the operation of digital circuits.
5. Simulate a subcircuit, a digital circuit which is inside a black box or entity, using the virtual laboratory software Proteus-ISIS. Capture a logic schematic in Proteus-ISIS and run its simulation to verify how it is functioning.
6. Install the ispLEVER Classic from Lattice Semiconductor and follow its design flow to implement a schematic/VHDL project into a sPLD chip.
7. Search books and the Internet to find information about the basics of VHDL language.
8. Explain the design flow of a modern digital circuit: from the VHDL description to the PLD programming.
9. Explain the basic technological details of a SPLD like the GAL22V10 and the way it is programmed.
10. Explain the differences between the VHDL design styles: structural and behavioural.
------Part 2------
11. Explain and relate the following concepts for designing a logic circuit: truth table, Boolean algebra and logic functions, minimisation, SoP (sum of products) and PoS (product of sums), canonical algebraic equations, minterms and maxterms. Design concept map.
12. Simplify or minimize logic function using software like Minilog.exe.
13. Find the datasheets of the Small and Medium Scale of Integration (SSI and MSI) integrated circuits.
14. Explain the concepts of flat design and hierarchical design (build using signals and components and their instantiation in VHDL language).
15. Simulate a logic circuit using ModelSim or ActiveHDL
------Part 3 ------
16. Design and use standard combinational circuit building blocks (at least one of them): multiplexers (or data selectors), demultiplexers (or distributors), binary decoders and encoders, decoders for hexadecimal to seven-segment LED displays, code converters, adders, comparators, etc.
17. Produce a concept map (or a mind map) to explain a topic on the subject, for instance, explain the advantages of using hardware description languages instead of electronic gate-level schematics.
18. Organise a plan for developing the exercise and being able to work efficiently cooperating in a team of 3 members using the proposed methodology.
19. Analyse your own individual and group study time.
20. Produce a quality written solution; for example, document your work using a predefined word processor template and utilities: spelling and grammar, chapter enumeration, page headers and footers, hyperlinks, cross-references, figure captions, text styles, etc., for a given exercise, control or any other assignment, using the given instructions.
21. Assess the own or the group learning progression and the quality of the deliverables.
1.5 Part 1: The basics (analysis)
1.5.1 Analysis of combinational circuit based on logic gates
Let’s start with the digital circuit in Fig. 1, a network of gates with 3 input signals and 2 output logic functions. As it can be seen, the circuit contains all kinds of gates. In this way, you’ll be able to study their functionality.
Fig. 1 Circuit to be analysed.
a) Analysing the circuit network, obtain the circuit equations. These Boolean algebraic expressions constitute the starting point of the analysis process which can be found in the Unit 1.3: Analysis of a digital circuit (analysis concept map).
1.5.2 WolframAlpha
b) Obtain the truth table, the product of minterms and the sum of maxterms using WolframAlpha (Wolfram Research). This outstanding software that calculates everything is going to be your first electronic design automation (EDA) tool, because it will save you the task of minimising the algebraic expression by hand, in the same way a digital calculator spares you the need to solve logarithms,s square roots and other complicated mathematical stuff.
Fig. 2 WolframAlpha computational engine.
c) Find other software that could be used to analyse or design digital circuits, for example, examining the Software section in our web page.
1.5.3 Installing and using Proteus-ISIS
d) Follow instructions in Unit 1.2 about installing and using Proteus-ISIS virtual laboratory. Open the tutorial exercise represented in Fig. 1 and run a simulation to analyse the way it works. Obtain its truth table and check if Proteus gives you the same result than WolframAlpha (Fig. 2). In the web pages will see several alternatives to the way of applying input signals, stimulus or test vectors. The idea behind the testing process is to verify all the truth table combinations.
e) Open the tutorial exercise represented in Fig. 1 and run a simulation to analyse the way it works. Obtain its truth table and check if Proteus gives you the same result than WolframAlpha. Thus, in this way you are going to be equipped with two very convenient software tools that will facilitate the design process of digital circuits. In the web pages will see several alternatives to the way of applying input signals, stimulus or test vectors. Fig. 3 shows an EasyHDL (Proteus scripting language) example, for inputting digital combinations to a circuit. The idea behind the testing process is to verify all the truth table combinations.
*SCRIPT GENERATOR TEST_SIGNALSPIN X[0..2]
FLOAT BITTIME = 1000m
// Here you are all the truth table.
// A binary combination every 1 s
X = 000
SLEEP FOR BITTIME
X = 001
SLEEP FOR BITTIME
X = 010
SLEEP FOR BITTIME
X = 011
SLEEP FOR BITTIME
X = 100
SLEEP FOR BITTIME
X = 101
SLEEP FOR BITTIME
X = 110
SLEEP FOR BITTIME
X = 111
*ENDSCRIPT
Fig. 3 Example of a Proteus script file automatically to apply all the 8 input combinations to a given circuit.
1.5.4 Installing and using ispLEVER Classic
Follow instruction in Unit 1.4 to install ispLEVER Classic for implementing projects into simple programmable logic devices (sPLD) like the GAL22V10. Check the software by running the following example design, which consist in a mix of schematics and VHDL files.
Basically, only two modules are needed to be installed, the software and the synthesiser Synplify:
· isp7_0m1_classic_ispLEVER.exe (the name will change accordingly to the version)
· SYN_p3.exe (Synplify Lattice version is a synthesiser tool from Synopsys)
One student of the group may also install the ispVMSystem in order to program the PROTOGAL board with the sPLD JED configuration file. A universal programmer[3] like the TopMax is another alternative (see Fig. 11b).
ispLEVER Project Navigator and the GAL22V10 device
A sample project in a zip file at the E1 web will be provided for checking the correctness of the software installation before attempting any design: a basic HEX-7SEG decoder. This is project of a combinational circuit corresponding to a hexadecimal to 7-segment decoder. It is built using a mix of schematics in the classical way and VHDL modules. Our aim is to synthesise it and generate the configuration JED file prepared to be downloaded into the simple programmable logic device (sPLD) GAL22V10. This is the most elemental sPLD from Lattice and a classic that has become a standard circuit for many years. It has a capacity around 500 gates and also contains 10 D-type flip-flops.
Execute “Project Navigator” and load the already defined initial project HEX-7SEG.
Fig. 4 Tutorial project HEX-7SEG to be loaded into the Project Navigator
Fig. 5 and Fig. 6 show the HEX-7SEG entity and internal architecture. Check our web for more information and designs from previous terms or similar subjects [1].
Fig. 5 HEX_7SEG Symbol or entity
f) Run the design flow process and finally, print and write some explanations about the final “*.jed” configuration file.
Analysing some circuit details of the example circuit
g) Deduce the truth table for the HEX-7SEG circuit and explain the way to connect a 7-segment LED display to their outputs. If your circuit has to be powered at 5 V, calculate the values of the segments’ limiting resistors.
The example presented here is a structured design which consists of 3 simpler blocks and some logic, as represented in Fig. 6. Take a look into SC2 and SC3 to see their internal design using gates, and then go into SC1, which corresponds to a VHDL design. So, the idea is that you can mix schematics and VHDL files in order to produce a more complex design. However, our aim is to focus the course in projects based only in VHDL.
h) Deduce, applying WorframAlpha, the truth table for the SC2 and SC3. Why are the signals M0, C0 and C1 used for?
Fig. 6 HEX_7SEG internal structure or architecture
i) Search Internet to read the GAL22V10 datasheet and study its architecture and the main technological characteristics. From the pdf, using the cut & paste tool, get 2 or 3 figures to document your work in addition to your own explanations. Which one of the seven different methods for implementing logic functions (NOT-OR-AND, NOT-AND-OR, NAND, NOR, method of decoders, method of multiplexers, ROM) is used in the GAL22V10? Which is the function of the programmable output logic macrocell?
Fig. 7 Device selector. Every project is associated to a programmable logic device. Select the GAL22V10 with the 24-pin package, the one which is included in Proteus-ISIS.
Synthesising the project
Compile the HEX-7SEG design and examine the following files: a) the configuration JED for the programmer and for the simulator; and b) the report file RPT where you can see, among others, the synthesised logic equations and the chip pin assignment (see Fig. 8). Every time you compile, you may get a different pin assignment distribution, especially if the VHDL source files are modified. This problem is solved in the case of CPLD and FPGA devices using a constrain file (or a pin-assignment tool) specifying at which pins do you want to connect the entity ports while synthesising.
Fig. 8 Pin assignment as seen in the report output file (RPT)
Simulating the circuit using Proteus-ISIS
Fig. 9 shows the way the project looks like once the simulation has been launched in Proteus-ISIS. The sPLD configuration file *.JED from the ispLEVER must be assigned the GAL22V10 device which is placed inside the decoder block. Simulate the circuit to check if everything is alright.