0806Filler_DFM.doc

@head: DFM Coverage Expanded at DAC’06

@text: Since 1999, Design-for-Manufacturability (DFM)issues have commanded center stage at DAC. While the phrase DFM was coined over a decade or more ago, its precise definition has variety as the understanding of DFM issues has grown. One has merely to look at the topic covered in this year’s DFM sessions to appreciate the breadth of the DFM challenge. For example, DFM papers focused on problems in the areas of design-litho interactions, design rule checking,enhanced corner-based design methodologies for improved analysis, and general modeling-optimization challenges.

Unlike DAC sessions of the past two years, the 2006 technical program containedsessions on statistical analysis, yield modeling and optimization in addition to topics that comprise traditional DFM topics. Here’s a sampling of technical sessions that focused on the broad topic of variability and design/technology interactions:

(1) Practical applications of DFM (session #5)

(2) Statistical timing analysis (session #10)

(3) Yield analysis and improvement (session #43)

(4) Design-technology interaction (session #45)

A brief overview of papers in Sessions #5 and #43 are given below. Then, the topic of design-technology interaction (e.g., Session #45) is examined in greater detail.

Papers presented inSession #5 (Practical Applications of DFM) addressed the issue of variation analysis methodologies. The first paper discussed the impact of process variation on SRAM yield and stability. The paper presented a methodology for analyzing the stability of SRAM bitcells in the presence of random fluctuations in device parameters. The authors presented a framework for characterizing the impact of process variations on the DC noise margin. They also provided models for estimating cell failure probabilities during read and write operations.

Chip-level statistical timing analysis and optimization required evaluation of path criticality at multiple process conditions. Process variations made circuit optimization difficult as critical path distribution varied across different process conditions. The next paper in the session proposed a new metric for robust circuit optimization and presented a novel algorithm to compute criticality probability every edge in the timing graph of a design. The approach presented in the paper could help speed up statistical timing analysis by ranking all paths according to their criticality in the variation space.

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