Collage Name : Dr. Subhahsh P. Chavda Ahir Kelvani Mandal's Group of Institutions

Junagadh

Subject Name : Fundamentals of Computer Organization

Subject Code : 610004

Semester : 1st

Logic Design

Flip – Flop

  • The flip flop is a bistable device, that is a circuit with only two stable states, which we designate the 0 state and the 1 state.
  • Each flip-flop has two outputs, Q and Q', and two inputs, set and reset.
  • This type of flip-flop is referred to as an SR flip-flop or SR latch.
  • When Q=1 and Q'=0, it is in the set state (or 1-state).
  • When Q=0 and Q'=1, it is in the clear state (or 0-state).
  • The outputs Q and Q' are complements of each other11/02/2011 and are referred to as the normal and complement outputs, respectively.
  • The binary state of the flip-flop is taken to be the value of the normal output.

Flip – Flop Design

GATED FLIP-FLOP :

  • The circuit shown below is a basic NOR latch.
  • The inputs are generally designated "S" and "R" for "Set" and "Reset" respectively.
  • Because the NOR inputs must normally be logic 0 to avoid overriding the latching

action, the inputs are not inverted in this circuit.

  • For the NOR latch circuit, both inputs should normally be at a logic 0 level.
  • Changing an input to a logic 1 level will force that output to a logic 0.
  • The same logic 0 will also be applied to the second input of the other NOR gate, allowing that output to rise to a logic 1 level.
  • This in turn feeds back to the second input of the original gate, forcing its output to remain at logic 0 even after the external input is removed.
  • The circuit shown below is a basic NAND latch.
  • The inputs are generally designated "S" and "R" for "Set" and "Reset" respectively.
  • Because the NAND inputs must normally be logic 1 to avoid affecting the latching action, the inputs are considered to be inverted in this circuit.
  • For the NAND latch circuit, both inputs should normally be at a logic 1 level.
  • Changing an input to a logic 0 level will force that output to a logic 1.
  • The same logic 1 will also be applied to the second input of the other NAND gate, allowing that output to fall to a logic 0 level.
  • This in turn feeds back to the second input of the original gate, forcing its output to remain at logic 1.

SR FLIP-FLOP :

  • The clocked SR flip-flop shown in Figure consists of a basic NOR flip-flop and two AND gates.
  • The outputs of the two AND gates remain at 0 as long as the clock pulse (or CP) is 0, regardless of the S and R input values.
  • When the clock pulse goes to 1, information from the S and R inputs passes through to the basic flip-flop.
  • With both S=1 and R=1, the occurrence of a clock pulse causes both outputs to momentarily go to 0.
  • When the pulse is removed, the state of the flip-flop is indeterminate, ie., either state may result, depending on whether the set or reset input of the flip-flop remains a 1 longer than the transition to 0 at the end of the pulse.

(a) Logic diagram(b) Truth table

MASTER - SLAVE FLIP-FLOP :

  • A master-slave flip-flop is constructed from two seperate flip-flops.
  • One circuit serves as a master and the other as a slave.
  • The master flip-flop is enabled on the positive edge of the clock pulse CP and the slave flip-flop is disabled by the inverter.
  • The information at the external R and S inputs is transmitted to the master flip-flop.
  • When the pulse returns to 0, the master flip-flop is disabled and the slave flip-flop is enabled.
  • The slave flip-flop then goes to the same state as the master flip-flop.

Logic diagram of a master-slave flip-flop

D FLIP-FLOP :

  • The D flip-flop is a modification of the clocked SR flip-flop.
  • The D input goes directly into the S input and the complement of the D input goes to the R input.
  • The D input is sampled during the occurrence of a clock pulse.
  • If it is 1, the flip-flop is switched to the set state (unless it was already set). If it is 0, the flip-flop switches to the clear state.

(a) Logic diagram with NAND gates(b) Graphical symbol Transition table

JK FLIP-FLOP :

  • A JK flip-flop is a refinement of the SR flip-flop in that the indeterminate state of the SR type is defined in the JK type.
  • Inputs J and K behave like inputs S and R to set and clear the flip-flop (note that in a JK flip-flop, the letter J is for set and the letter K is for clear).
  • When logic 1 inputs are applied to both J and K simultaneously, the flip-flop switches to its complement state, i.e. if Q=1, it switches to Q=0 and vice versa.
  • Output Q is AND with K and CP inputs so that the flip-flop is cleared during a clock pulse only if Q was previously 1.
  • Similarly, Output Q' is AND with J and CP inputs so that the flip-flop is set with a clock pulse only if Q' was previously 1.

(a) Logic diagram with NAND gates(b) Graphical symbol Transition table

T FLIP-FLOP :

  • The T flip-flop is a single input version of the JK flip-flop.
  • T flip-flop is obtained from the JK type if both inputs are tied together.
  • The output of the T flip-flop "toggles" with each clock pulse.

(a) Logic diagram with NAND gates(b) Graphical symbol Transition table

Edge Triggered FLIP-FLOP :

Another type of flip-flop that synchronizes the state changes during a clock pulse transition is the edge-triggered flip-flop.

When the clock pulse input exceeds a specific threshold level, the inputs are locked out and the flip-flop is not affected by further changes in the inputs until the clock pulse returns to 0 and another pulse occurs.

Some edge-triggered flip-flops cause a transition on the positive edge of the clock pulse (positive-edge-triggered), and others on the negative edge of the pulse (negative-edge-triggered).

D-type positive-edge triggered flip-flop

Triggering of Flip-flops :

The state of a flip-flop is changed by a momentary change in the input signal. This change is called a trigger and the transition it causes is said to trigger the flip-flop.

The clock pulse goes through two signal transitions from 0 to 1 and the return from 1 to 0.

Positive transition is defined as the positive edge and the negative transition as the negative edge.

Definition of clock pulse transition

Transfer Circuit

  • Let us examine the operation of this flip-flop in a configuration called a transfer circuit.
  • In this figure shows two set of flip-flops named X1, X2, X3 and Y1, Y 2, Y 3.
  • The function of the configuration is to transfer the state, or contents, of Y1intoX1 , Y2 into X2,Y3 into X3 upon the TRANSFER command which consist of a 1 on the TRANSFER line.
  • Assume that Yx, Y2, and Y3have been set to some states that we want to remember, or store, in Xx, X2, and X3, while the Y flip-flops are used for furthercalculations.
  • Placing a 1 on the TRANSFER line will cause this desired transfer of information. Understanding the transfer of the state of y, into X, depends on seeing that if F, is in the 0 state, the Yxoutput line has a 0 on it, and so the input line connected to the AND gate will be a 0 and the AND gate will place a 0 on the S input line of X, while the Y1output from Y1will be a 1, causing, in the presence of a 1 on the TRANSFER line, a 1 on the R input of X1.
  • Similar reasoningwill show that a l in Y1will cause a I to be placed in X, in the presence of a l on the TRANSFER line.
  • As long as the TRANSFER line is a 0, both inputs to the X flip-flops will be 0s, and the flip-flop will remain in the last state it assumed.
  • The above simple operation, the transfer operation, is quite important. Related sets of flip-flops in a computer are called registers, and the three flip-flops Yu Y2, and K3 would be called simply register Y, and the three flip-flops, X,, X2, andX3 would be called register X. Then a l on the TRANSFER line would transfer the contents of register Y into register X. This is an important concept.

Clocks

  • A very important fact about digital computers is that they are clocked.
  • This means that there is some "master clock" somewhere sending out signals which are carefully regulated in time.
  • These signals initiate the operations performed.
  • The clock is, therefore, the mover of the computer in that it carefully measures time and sends out regularly spaced signals which cause things to happen.
  • We can examine the operation of the flip-flops and gates before and after the clock "initiates an action." Initiating signals are often called, for historical reasons, clock pulses.
  • The clock waveform in Figure is called a square wave.
  • The figure shows two important portions of a square wave the leading edge, or rising edge, or sometimes positive-going edge,and the falling edge, or negative-going edge.

Shift Register

  • This circuit accepts information from some input source and then shifts this information along the chain of flip-flops, moving it one flip-flop each time a positive-going clock signal occurs.
  • Shift registers are a type of sequential logic circuit, mainly for storage of digital data.
  • They are a group of flip-flops connected in a chain so that the output from one flip-flop becomes the input of the next flip-flop.
  • Most of the registers possess no characteristic internal sequence of states.
  • All the flip-flops are driven by a common clock, and all are set or reset simultaneously.


4-Bit Shift Register(SIPO) :

  • The effect of each clock pulse is to shift the data contents of each stage one place to the right, and this is shown in the following table until the complete data value of 0-0-0-1 is stored in the register.
  • This data value can now be read directly from the outputs of QA to QD. Then the data has been converted from a serial data input signal to a parallel data output.
  • The truth table and following waveforms show the propagation of the logic "1" through the register from left to right as follows.

Clock Pulse No / QA / QB / QC / QD
0 / 0 / 0 / 0 / 0
1 / 1 / 0 / 0 / 0
2 / 0 / 1 / 0 / 0
3 / 0 / 0 / 1 / 0
4 / 0 / 0 / 0 / 1
5 / 0 / 0 / 0 / 0

Summary of Shift Registers

  • Then to summaries.
  • A simple Shift Register can be made using only D-type flip-Flops, one flip-Flop for each data bit.
  • The output from each flip-Flop is connected to the D input of the flip-flop at its right.
  • Shift registers hold the data in their memory which is moved or "shifted" to their required positions on each clock pulse.
  • Each clock pulse shifts the contents of the register one bit position to either the left or the right.
  • The data bits can be loaded one bit at a time in a series input (SI) configuration or be loaded simultaneously in a parallel configuration (PI).
  • Data may be removed from the register one bit at a time for a series output (SO) or removed all at the same time from a parallel output (PO).
  • One application of shift registers is converting between serial and parallel data.
  • Shift registers are identified as SIPO, SISO, PISO, PIPO, and universal shift registers.

Binary Counter

  • The fundamental purpose of the binary counter is to record the number of occurrences of some input.
  • This is a basic function, that of counting, and it is used over and over.
  • The first type of binary counter to be explained is in Figurethis counter records the number of occurrences of a positive-going edge (or pulse) at the input.
  • A binary counter is a machine (like a computer) which counts in binary.
  • A group of people can become a binary counter, and it's a good way to see how the number system works.
  • Line up in a row, with everyone's right arm horizontal, so their hand touches the shoulder of the next person.
  • The person on one end is the unit and has to do the most work.
  • This is on their left-hand end of the line (but looks like our right, as we're facing them).
  • The child on the other end does no work at all, but merely provides a shoulder! There are only two rules.
  • Type of Binary counter :
  • Asynchronous Binary Counter OR Ripple Counter
  • An asynchronous (ripple) counter is a single K-type flip-flop, with its J (data) input fed from its own inverted output.
  • This circuit can store one bit, and hence can count from zero to one before it overflows (starts over from 0).
  • This counter will increment once for every clock cycle and takes two clock cycles to overflow, so every cycle it will alternate between a transition from 0 to 1 and a transition from 1 to 0.
  • Notice that this creates a new clock with a 50% duty cycle at exactly half the frequency of the input clock.
  • If this output is then used as the clock signal for a similarly arranged D flip-flop (remembering to invert the output to the input), you will get another 1 bit counter that counts half as fast. Putting them together yields a two bit counter:

• Notes

  1. called asynchronous because the C1 inputs of the flip-flopsare not all

driven by the same (CLOCK) signal

2. each output depends on a change in the previous flip-flopsoutput

3. sometimes called a ripple counter because the data "ripples"from

4. the output of one flip-flop to the input of the next

5. can also be implemented in JK

  1. Synchronous Binary Counter
  • A simple way of implementing the logic for each bit of an ascending counter (which is what is depicted in the image to the right) is for each bit to toggle when all of the less significant bits are at a logic high state.
  • For example, bit 1 toggles when bit 0 is logic high; bit 2 toggles when both bit 1 and bit 0 are logic high; bit 3 toggles when bit 2, bit 1 and bit 0 are all high; and so on.
  • All flip-flops clocked with the same signal

1.hence all outputs change simultaneously

  • the sequence of the count is controlled by combinationallogic

3.sometimes called the state sequence

4.note that synchronous binary counters use both sequential and

5.combinational elements

  • 4 – Bit Binary Counter :
  • In the 4-bit counter to the right, we are using edge-triggered master-slave flip-

flops similar to those in the Sequential portion of these pages.

  • The output of each flip-flop changes state on the falling edge (1-to-0

transistion) of the T input.

  • The count held by this counter is read in the reverse order from the order in which the flip-flops are triggered.
  • Thus, output D is the high order of the count, while output A is the low order.
  • The binary count held by the counter is then DCBA, and runs from 0000 (decimal0) to 1111 (decimal15).
  • The next clock pulse will cause the counter to try to increment to 10000 (decimal16).
  • However, that 1 bit is not held by any flip-flop and is therefore lost.
  • As a result, the counter actually reverts to 0000, and the count begins again.

BCD Counter

  • The binary counters considered so far all count to their limit before resetting to all 0s.
  • Often it is desired to have counters count in binary-coded decimal (BCD).
  • Figure shows a typical BCD counter.
  • Examination of this counter shows that it counts normally until it reaches 1001 that is, the sequence until that time is as follows:
  • When the next negative-going edge at the input occurs, however, the BCD counter returns to all Os.
  • At the same time (that is, during the interval when the counter goes from 9 to 0) a negative-going signal edge occurs at the CARRY output.
  • This CARRY output can be connected to the INPUT of another BCD counter, which will then be stepped by 1 when the first BCD stage goes from 9 to 0.
  • This is shown in Figure where several four-flip-flop BCD stages are combined to make a large counter.

Arithmetic Logic Unit

Construction of the ALU

  • The arithmetic-logic unit (ALU) performs allarithmetic operations (addition, subtraction,multiplication, and division) and logic operations.
  • Logic operations test various conditions encounteredduring processing and allow for different actions to betaken based on the results.
  • The data required to performthe arithmetic and logical functions are inputs from thedesignated CPU registers and operands.
  • The ALU relies on basic items to perform itsoperations.
  • These include number systems, data routingcircuits (adders/subtracters), timing, instructions,operands, and registers.
  • Figureshows arepresentative block diagram of an ALU of amicrocomputer.

  • CONTROL UNIT:
  • The control unit maintains order within thecomputer system and directs the flow of traffic(operations) and data.
  • The flow of control is indicatedby the dotted arrows on figure.
  • The control unitselects one program statement at a time from theprogram storage area, interprets the statement, andsends the appropriate electronic impulses to thearithmetic-logic unit and storage section to cause themto carry out the instruction.
  • The control unit does not perform the actualprocessing operations on the data.
  • Specifically, thecontrol unit manages the operations of the CPU, be it asingle-chip microprocessor or a fill-size mainframe.
  • Like a traffic director, it decides when to start and stop(control and timing), what to do (program instructions),where to keep information (memory), and with whatdevices to communicate (I/O).
  • It controls the flow of alldata entering and leaving the computer.
  • It accomplishesthis by communicating or interfacing with thearithmetic-logic unit, memory, and I/O areas.
  • Itprovides the computer with the ability to function underprogram control.
  • Depending on the design of thecomputer, the CPU can also have the capability tofunction under manual control through man/machineinterfacing.
  • PRIMARY STORAGE (MAIN MEMORY)
  • The primary storage section (also called internalstorage, main storage, main memory, or just memory)serves four purposes:To hold data transferred from an I/O device to theinput storage area, where it remains until thecomputer is ready to process it.
  • This is indicatedby the solid arrow on figure. To hold both the data being processed and theintermediate results of the arithmetic-logicoperations.
  • This is a working storage areawithin the storage section. It is sometimesreferred to as a scratch pad memory.
  • To hold the processing results in an outputstorage area for transfer to an I/O device.

Integer Representation