A) the Circuit Design Using NAND Gates (1 Point

NAME:

1. For an S-R latch with enable specify:

(a) The circuit design using NAND gates (1 point)

(b) The function table (1 point)

2. For a negative-edge-triggered D flip-flop, show:

(a) The circuit design using D latches (1 point)

(b) The function table. (1 point)

(c) Define setup and hold time for this flip-flop (1 point) and illustrate setup and hold time on a timing diagram of this flip-flop. (1 point)

3. Draw the logic diagram of the following circuits:

(a) A 4-bit serial-in serial-out shift register (1 point)

(b) A 4-bit parallel-in parallel-out shift register (1 point)

(c) A 4-bit bidirectional shift register, i.e., it can shift data in both directions (right shift and left shift) (1 point)

4. Design a clocked synchronous state machine with one input, X, and two outputs, UNLK and HINT. The UNLK output should be 1 if and only if X is 0 and the sequence of inputs received on X at the preceding clock ticks was 1011000. The HINT output should be 1 if and only if the current value of X is the correct one to move the machine closer to being in the “unlocked” state (with UNLK=1). Points are given as follows:

(a) State and output table (1 point)

(b) Transition/excitation and output table for synthesis with D flip-flops (1 point)

(d) The state diagram of the state machine (1 point)

5. Design a clocked synchronous state machine with one input, X, and one output, Z. The output should be 1 if the number of 0 inputs on X since reset is a multiple of 6, and 0 otherwise.

Following items are required:

(a) State and output table (1 point)

(b) Transition/Excitation table for synthesis with D flip-flops (1 point)

(e) Logic diagram for implementation with D flip-flops (1 point)

(f) Excitation maps, using the minimal cost approach and J-K flip-flops. (1 point)

6. Draw the structure for a clocked synchronous Mealy machine (1 point).

NAME:

1. For a D latch specify:

(a) The circuit design using NAND gates (1 point)

(b) The function table (1 point)

2. For a positive-edge-triggered D flip-flop, show:

(a) The circuit design using D latches (1 point)

(b) The function table (1 point)

(c) Define setup and hold time for this flip-flop (1 point) and illustrate setup and hold time on a timing diagram of this flip-flop. (1 point)

3. Draw the logic diagram of the following circuits:

(a) A 4-bit asynchronous binary counter constructed only with flip-flops (and no other components) (1 point)

(b) A 4-bit synchronous binary counter constructed with T flip-flops with enable inputs and gates (1 point)

(c) A 4-bit synchronous up/down counter: it counts in ascending or descending order depending on input signal UP/DOWN (1 point)

4. Design a clocked synchronous state machine with one input, X, and two outputs, UNLK and HINT. The UNLK output should be 1 if and only if X is 0 and the sequence of inputs received on X at the preceding clock ticks was 0011000. The HINT output should be 1 if and only if the current value of X is the correct one to move the machine closer to being in the “unlocked” state (with UNLK=1). Points are given as follows:

(a) State and output table (1 point)

(b) Transition/excitation and output table for synthesis with D flip-flops (1 point)

(d) The state diagram of the state machine (1 point)

5. Design a clocked synchronous state machine with one input, X, and one output, Z. The output should be 1 if the number of 0 inputs on X since reset is a multiple of 5, and 0 otherwise.

Following items are required:

(a) State and output table (1 point)

(b) Transition/Excitation table for synthesis with D flip-flops (1 point)

(e) Logic diagram for implementation with D flip-flops (1 point)

(f) Excitation maps, using the minimal cost approach and J-K flip-flops. (1 point)

6. Draw the structure for a clocked synchronous Moore machine (1 point).