Course:ACOE361 – Digital Systems DesignDate:28/01/10 Time: 2 1/2 hours

Instructions to candidates: Attemptfour out of five questions, and indicate which ones you intend to answer. Use the separate answer sheets. All questions carry equal marks.No notes or printed material is allowed.

Question 1:

Write the structural VHDL code creating the circuit of Figure 1. Specify the

  1. Top-level Entity(5 marks)
  2. Architecture (component declaration)(5 marks)
  3. Architecture (signal declaration)(5 marks)
  4. Architecture (component instantiation)(10 marks)

assuming all components have been precompiled.

Figure 1

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Question 2:

The circuit implementing the state machine of Figure 2 has a single input (X) and a single output (Y) and should be self-correcting.

(a)Give the state transition table(10 marks)

(b)Describe in VHDL the circuit that implements the following state diagram (Figure 2). Specify the

  1. Entity(5 marks)
  2. Architecture (type and signal declarations)(2 marks)
  3. Architecture (state memory)(3 marks)
  4. Architecture (next state, output logic)(5 marks)

Figure 2

Question 3:

a)Describe the circuit shown below (Figure 3) in VHDL. Specify both entity and architecture (15 marks)

b)Write an appropriate VHDL testbench for logic simulation.(10 marks)

Figure 3

Question 4:

(a)Draw the circuit that will be produced by synthesizing the following VHDL code fragment: (10 marks)

signal a, b, c: std_logic;

signal out_r: std_logic;

begin

process(clk, rst_n)

begin

if rst_n = ‘0’ then

out_r <= ‘0’;

elsif rising_edge(clk) then

if c = ‘0’ then

out_r <= a AND b;

else

out_r <= a OR b;

end if;

end if;

end process;

end;

(b)Find the errors in the following VHDL code fragment. Indicate if it is a syntax error or a synthesis error and its effect on simulation/synthesis (15 marks)

Architecture rtl of q4 is

signal a: std_logic_vector(3 downto 0);

signal b, d: std_logic;

signal c: std_logic_vector(5 downto 0);

begin

a <= ‘0100’;

b <= “0”;

process(d)

begin

if d = ‘1’ then

c <= “11”&a;

end if;

end process;

c <= ”00”&a + b;

end;

Question 5:

(a)Answer the following questions:(15 marks)

1. The VHDL assignment a <= b**c; where, a, b and c are appropriate input and output signals can be:

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  1. Simulated and synthesized
  2. Simulated but not synthesized
  3. Synthesized but not simulated
  4. Neither simulated nor synthesized

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2. The proper sequence of steps in a digital system design flow is

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  1. Synthesis, HDL description, simulation
  2. HDL description, simulation, synthesis
  3. Simulation, synthesis, HDL description
  4. HDL description, synthesis, simulation

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3. What probably happened, when a signal appears to have a value of ‘U’ in simulation?

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  1. The signal was never assigned a value
  2. The signal was assigned multiple values
  3. The signal is missing from a process sensitivity list
  4. The signal is mistakenly placed in a process sensitivity list

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4. The sensitivity list of a process describing a 2-to-4 decoder should include:

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  1. one signal
  2. two signals
  3. three signals
  4. four signals

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5. An FPGA basic logic element is composed of:

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  1. Decoders, multipliers, and dividers
  2. Compilers, assemblers, and debuggers
  3. ALUs, control logic, and memory
  4. LUTs, F/Fs and multiplexers

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(b) Describe a rising edge triggered T flip-flop in VHDL(10 marks)

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