CPSC 465 Integrated Circuit Design
Lab 6
MOSIS Padframe and fabrication
Purpose:
- learn to use MOSIS padframe,
- learn to run Design rule check, prepare CIF format for fabricaiton
- learn Magic hierarchy commands
- learn to use Synopsys Hspice, Awave tools for simulate circuit for delay, power metrics
Required materials:
- Magic layout tool on Unix Server
- Hspice, Avant Waves tools from Synopsys tools set
- Text editor(nedit on the Unix box or your favorite ASCII editor)
Lab steps:
- Verify your decoder design from lab 4, correct as instructor suggested.
Similar as IIT cell boundary convention, but our cell can have height about 80 lamda.
You may use vertical transistor(if sizing needed, since the cell height can not change),consult with instructor for this.
- Make a new directory in your magic directory:
mkdir chip-decoder
cd chip-decoder
cp usr/user/ocf/zhao/magic/chip/*mag . (magic pad frame layouts are mainly from)
mv ../decoder/decoder.mag . (copy your verified decoder layout here)
magic –T SCN3ME_SUBM.30 padframe-yourName (no .mag extension here)
In Magic window, use Magic hierarchy commands:
:getcell decoder (no .mag extension; do not move .ext files to other directory, they are used by other .ext files when you using cell hierarchy)
:expand (shortcut key: type x)
( select one of the instance, and expand the cell)
:edit (select the cell and type ‘edit’)
:write (save the layout)
You can use
:dump to copy your design to the padframe too.
Note: difference between “:dump vs. :getcell”: like copy as text vs. object in Microsoft Word.
Wire s1, s2 from PadIn550_0, _1, label S0_in, S1_in from bottom, add 2 invertersbefore s1, s2 feed into the decoder. Add 2 inverters to output d0-d3 respectively, then wire the output of inverters to PadOut550_0, ..,-3 respectively(several blue M1 on top), label d0_out, .., d3_out on the pads respectively.
3.
Verify the design with the padframe, it must beDesign Rule Check free/ extraction free. Once fabricate, any mistake will cause the design to fail.
Design rule check:
:extract all
:drc check
:drc count
:drc find 1
Run ":drc check" to recheck the whole design, and ":drc count" to tell you how many design rule errors you have; run “:drc find 1”, then use the ‘center’ key (‘5’ on the right side on keyboard under 8, above 2), the drc error in white dot will be centered in the screen, then use ‘v’ to enlarge it.
Extraction warning
If two nodes in a cell have the same name, yet are not connected by any wires,
Magic will still consider them to be “virtually” connected together.
(The “benefit” of this virtual connection is that it allows you to connect the two nodes at a higher level of hierarchy.)
Magic will extract layout like this normally, but will also spit out a warning.
DO NOT USE THESE VIRTUAL CONNECTIONS
...your extraction MUST be clear of all warnings.
To check the warnings, go to the top level of your design and ":extract all" and you see warnings or error. Extraction problems are be viewed by type "feedback count" .
:extract all
:feedback count
:feedback find 1
:feedback clear
4. Create CIF
Foundries make chips using lithographic masks. But the paint we drew in Magic doesn’t
exactly correspond to these masks.
So we need Magic to create the masks from the paint that we drew.
The masks needed include active, well, implant, etc. and are in Caltech
Intermediate Format (CIF).
:cif ostyle lambda=0.30(c)
:cif write project
:quit
Now create a new directory, copy the CIF file there, and read it back into magic to make sure that there are no final Design Rule Errors due to the creation of the well regions.
mkdir finalchip
cp project.cif finalchip
cd finalchip
magic
:cif istyle lambda=0.30(c)
:cif read project
Check for Design Rule Errors, and correct if necessary.
:writeall
:quit
You will now have the final magic files with corrections. Start Magic again and create a final CIF file if corrections were made.
:cif ostyle lambda=0.30(c)
:cif write submit
:quit
Other good suggestions are at:
Checksum:
gcc mosiscrc.c
a.out –t <CIF file name>
5.Submit to MOSIS. Test after get fabricated design, and write a report submitted to MOSIS.
Lab report
Hand in a clear, concise report between 1.5- 3 pages
- Print the magic layouts of the decoder with top output pads, using PringScreen on keyboard to get the layout graph.
- Hand in the waveform of the decoder with the padframe( In awaves, choose Window/ stack overlay mode )with s1, s0, as well as output, d0-d3, using PrintScreen to get the graph too.
- Describe any problems you encounter. Also hand in the Hspice input file.
- Record delay, power. Explaining the results of the analysis of wave form, show the relation to the truth table.
- Draw chip pin graph. Write a test plan. Test after get fabricated design, and write a report submitted to instructor and later to MOSIS.
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Appendix
1. Fan in: limited to 3-4 inputs at most
Large fan out consideration: insert buffer
2.Debug:
•Divide design into small parts to isolate the problem area, simulate small blocks, connect them together before lay out a big design, say 16x16 bit multipler.
•Check layout:
If you get error message mentioning a node name like a_n10_80,
:goto nodename
then zoom out a few times to see where you are. Similar results with:
:findlabel nodename
How do you know know what Magic will call a node in the layout?
Select the wire in which you are interested
:getnode
•Check waveform:
Hspice + awave = Oscilloscope
Check waveform, specially the internal nodes on the critical path.
•Using IRSIM for big design: verify functionality, quick than Hspice.
3.Sizing: Tilos algorithm
4.
5,Tale of an IC Engineer,
This purpose of this journal is document a simple full custom IC design project
from the beginning to end in order that students new to the field of IC design might learn
about the IC design process vicariously before they embark on a project for themselves.
The idea that since student time is in short supply, students should have a design
reference showing all the pitfalls of the design process so they do not waste time making
mistakes common among novices.