Design of 1V Opamp Using Standard Digital CMOS Technology

Vikas Agarwal

Ritesh Parekh

Indian Institute of Science, Center for Electronic Design and Technology

Bangalore - 560012

Abstract – This paper addresses the issues involved in designing 1V Op-amp in standard digital CMOS technology. Bulk-driving technique is used to circumvent the metal–oxide semiconductor field-effect transistor turn-on (threshold) voltage requirement. The Op-amp will be designed in a Europractice 0.7m n-well CMOS process having threshold voltage of 0.76V and –1V for NMOS and PMOS respectively. Simple and cascode bulk driven current mirror are designed in which all transistors are operated in saturation instead of linear as proposed in [1]. This helps in achieving great degree of matching. A 1V bulk driven Op-amp is designed using this cascode current mirror. The open-loop gain of the amplifier is 67.5dB, the gain bandwidth product is 584KHz and phase margin is 48.5. Power Consumption of the opamp is 20W.

I. Introduction

Rapid growth of portable applications promotes battery operation that favors low voltage and low power circuits. This suggests that in near future, for implementation of mixed analog-digital design, power supply of 1.5V or less will be used.

In mixed-signal design the analog portion of the circuit is operated with the same supply voltage as the digital part. Digital applications such as microprocessor and memories, drives technology scaling and reduced power supply. This is to achieve higher speed and reduce power consumption. However with technology scaling, threshold voltage does not scale down proportionally because this would lead to increased leakage current. This implies that the low voltage analog designs are incompatible with the CMOS technology trends of the future. Hence many of the conventional analog circuit topologies fail to operate due the reduced power supply. This poses a great challenge to CMOS analog/mixed-signal circuit design. To overcome the problem there are three possibilities. One way is to multiply the lower voltage dc to larger values or to modify existing CMOS technologies to accommodate low-voltage analog design. A better approach is to develop new circuit technique that can achieve the objective with existing technology.

This paper focuses on developing analog circuit technique that is compatible with future CMOS technologies. Note that circuit techniques that permit low voltage operation with large thresholds offer the potential for more thoroughly utilizing the technology at any voltage range even if low threshold voltage technologies become standard.

II. Bulk – Driven MOSFET

A limitation to implementing analog circuits at low voltage is the threshold voltage. The metal–oxide semiconductor field-effect transistor (MOSFET) must be turned on in order to perform any type of signal processing. This implies that for CMOS technology the power supply must satisfy the following requirement for strong inversion operation,

VDD + |VSS|  VGS = VDSat + |VT|

where,

VDD is the positive power supply,

VSS is the negative power supply and

VT is the magnitude of the largest threshold of the NMOS or PMOS transistors.

Furthermore with gate driving the MOSFET, the supply voltage requirement becomes,

VDD + |VSS|  VGS = VDSat + |VT| + Vsig

The turn-on or threshold voltage requirement ultimately constrains signal swing and consequently dynamic range. If the MOSFET is bulk-driven, then the voltage overhead associated with VT can be removed from the signal path.

Fig. 1 illustrates a PMOS structure cross section where an n-well process is assumed.

Fig 1. Cross-section of a PMOS transistor and terminal voltages for bulk source operation

As shown in Fig. 1 the gate-source potential is taken to a dc voltage that is sufficient to turn on the MOSFET. The signal is applied between the bulk and the source. The current flowing from the source to drain is modulated by the reverse bias on the bulk channel junction. The result is a junction field-effect transistor (shown in Fig. 2) with the bulk as the signal input (gate). Consequently, a high input impedance depletion-mode device results.

Fig 2. Bulk driven PMOS transistor

Fig 3. Transfer characteristics for bulk driven PMOS transistor

As shown in transfer characteristics (Fig. 3) the drain current varies linearly with VSB ( 0V). Also bulk current is in picoampere range for VSB 0.8 V.

BSIM Model 3 equations of the drain current iD of a MOSFET are

=

for

and

for

However to describe bulk-source operation, the VT term in above equations should be expanded.

for

and

for

III. Bulk – Driven Current Mirrors

Conventional current mirror contain gate-drain, or diode connections. The voltage drop across this connection is greater than |VT| for the strong- inversion saturation operation. The bulk driven current utilizes a bulk-drain connection to avoid the large voltage drop penalty. As a result this current mirror is suited for low power supply voltage applications.

Fig 4. PMOS bulk-driven current mirror


With reference to Fig. 4, M1 is operated in linear region and M2 is operated in saturation [1]. The output current expression is given by

However if M1 is operated in saturation, then, the output current expression is same as conventional current mirror i.e. ratio of W/L's. M1 can be operated in saturation if VTP is approximately equal to VDD. For Europractice 0.7m technology VTP = -1V, hence M1 can be operated in saturation.

Fig 5. Simulation results of bulk driven current mirror
Iin / Iout (expected) / Iout (Simulation)
4 / 4 / 4.17
5 / 5 / 5.142
6 / 6 / 6.089
7 / 7 / 7.151
8 / 8 / 8.18
9 / 9 / 9.18

Table 1. Bulk-Driven current mirror simulated performance and expected results.

The difference in simulated results and theoretical results are due to VDS mismatch. Output resistance of simple current mirror is measured to be of the order of 5 Meg.

Fig 6. Bulk Driven Cascode Current Mirror

Fig 7 Simulation results of Bulk Driven Cascode Current Mirror

Iin / Iout (expected) / Iout (Simulation)
3 / 3 / 3.13
4 / 4 / 4.042
5 / 5 / 5.023
6 / 6 / 5.966

Table2. Bulk-Driven Cascode current mirror simulated performance and expected results.

Output resistance of Cascode current mirror is of the order of 150 Meg.

IV. Bulk – Driven OPAMP

Fig8. Bulk Driven Op-amp

The designed Op-amp with bulk-driven input transistors is shown in Fig. 8. Because an n-well CMOS process is used, the bulk driven transistors are only of PMOS-type. The input stage consists of bulk-driven differential pair, M5-M6 loaded by the NMOS current mirror. The Op-amp is biased with a single current reference Iref. Tail current of differential pair is provided by bulk driven cascode current mirror discussed in section III. The second stage of opamp consists of Common source amplifier with constant current source load. RZ and CC are the compensation elements for the miller pole-splitting technique. The Op-amp gain bandwidth product and dc open loop gain are described by

A total quiescent power dissipation of 20W is achieved with the selected current bias of 5A. Another goal was to minimize input referred noise. The noise at low frequencies is dominated by 1/f noise. Choosing fairly large values for the channel width and length of the input transistors M5-M6 minimizes this noise.

V. Simulation Results

The simulated performance of the 1V CMOS rail-to-rail Op-amp is given in Table 3. The Op-amp has the dc open loop gain of 67.53dB, phase margin of 48.56 and unity gain frequency of 584.11 kHz at a mid-supply common mode voltage. The measured frequency response is presented in fig 9.

Fig9. Open loop gain at mid-supply common mode voltage.

Parameter / Simulated results
DC open loop gain / 67.53dB
IDD (Supply current) / 20µA
Unity gain Frequency / 544.11kHz
Phase margin / 48.56
ICMR / 0.3 to 1V
CMRR / 60dB at 1kHz

Table3. Bulk-Driven Cascode current mirror simulated performance and expected results. Note VDD = 1V, VSS = 0, VCM = 0.5V

Fig10. Open loop gain AO as a function of input common mode voltage.

Fig11. Common Mode Rejection ratio Vs Frequency


The input common mode range is from 0 to 1V. However below 0.3 V bulk current increases significantly, because the tail voltage is not able to follow the input common mode voltage.

VI. Conclusion

The use of bulk driven devices makes it possible to design low-voltage opamps with large input CMR and low power consumption in standard CMOS technology. In this paper simple current mirror, cascode current mirror and two stage bulk driven opamp is described and the simulation results are given. For the current mirror the input transistor is operated in saturation region instead of linear region as done in [1]. This gives better matching between the input and output current. The gain of the opamp is 67.53 dB and GBW is 584 kHz. The power consumption is 20µW.

References

[1] B. J. Blalock and P. E. Allen, “A low-voltage, bulk-driven MOSFET current mirror for CMOS technology,” in Proc. 1995 ISCAS, vol. 3, pp. 1972–1975.

[2] C. Hu, “Future CMOS scaling and reliability,” Proc. IEEE, vol. 81, pp. 682–652, May 1993.

[3]. B. J. Blalock and P. E. Allen, “A one-volt, 120-_W, 1-MHz OTA for standard CMOS technology,” in Proc. ISCAS, 1996, vol. 1, pp. 305–307.

[4] P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design. New York: Holt, Rinehart and Winston, 1987.

Fig12. InputCommonModeRange