CMU-PNPI group.
Presented by N.Bondar
Anode electronics current status.
(February 17-19)
CMP16_D and CMP16_E chip bench test result.
Del16 delay chip status
AD16 board
CMP16_F chip status
Anode front-end electronics integration issue
Radiation test.
CMP16_D and CMP16_E chip bench test result.
CMP16_D and CMP16_E was submitted in September to AMI 1.2 microns technology via MOSIS. Indeed CMP16_E chip is the same like CMP16_D, but delay circuit was removed.
Reason for these two submissions is to compare chip with and without delay inside the chip.
Also few small changes was added in scheme of the chip to improve channel to channel isolation and to remove unnecessary external bias voltages.
Results of “on bench” measurements are presented in the next table:
CMP16_DCMP16_E
Amplifier gain9mV/fC9mV/fC
Equivalent input noise
@Cin=0 pF0.6fC 0.6fC
@Cin=200pF1.5fC1.5fC
Minimum available threshold
@Cin = 200pF20 fC20fC
Threshold control range0fC - 100fC0fC - 100fC
Delay:
minimum95ns 85ns
maximum125ns controllable 87ns
Slewing time3ns3ns
Output pulse width 20ns - 150ns “ width over threshold”
adjustable
Internal Cross-talk
(worst case)1.5% anal. + 2.5fC dig.1.5% anal. + 0.2fC dig.
Resume:
Both of them CMP16_D and CMP16_E has almost the same characteristics, but chip CMP16_E has:
less internal delay for 10ns,
less internal cross-talk from “digital” part 0.2fC against 1.0fC.
One more detail – there are
only 3 broken chips of 14 for CMP16_E,
but - 6 broken chips of 14 for CMP16_D.
That is obvious that CMP16_E chip significant better than previous samples.
Ad16 board
Introduction
AD16 board is a 16 channels amplifier-discriminator board for Cathode Strip Chamber (CSC).
This board is designed for direct connection to the chamber.
This board has 34 pins input connector and 40 pins output connector.
During standard working situation this board is connected to ALCT board with a 20 twisted pair cable. This cable is used both to transmit output signals to ALCT and to supply the board with power voltage, threshold voltage and test pulsing. All these voltages are produced by ALCT device.
For testing anode electronics with TDC a special LVDS/ECL converter module will design. This converter will receive LVDS signal and transmit them in ECL standard to ADC. Also the module will supply AD16 board with power and threshold voltages.
Threshold voltage must have possibility of manual adjustment and easy monitoring.
AD16 board specification:
Board dimensions 2.8" x 3.075" x 0.625"
Input connector strip socket, two row, 34 contacts
Output connector 40 pins header.
Inputs DC isolated
Output current source LVDS compatible
Power supply voltage +5.5V
Minimum +4V
Maximum +6V
Current 0.1A @+5.5V
Threshold voltage 0 - 1.7V control range
0 - maximum threshold
Test pulse:
termination110 Ohm
Test pulse-charging0.25mV/fC
Maximum pulse amplitude 2V
Foolproof features: Wrong connection AD16 board with chamber does not damage neither board nor protection board.
Wrong polarity of output cable will not damage AD16 board if all signals and voltages are within standard levels.
Assembling drawing and actual size of the board is in
file: AD16_assembl.ps
Input and Output connector specification is in a circuit diagram of the board - file: AD16_p1.ps
Production conditions.
AD16 board will be assembled, debugged and tested during production flow.
Each board must have its Unicode.
Minimum necessary parameters for the production flow measurement will be extracted. Results of the measurements will be placed in a database.
CMP16_F chip status
In the very end of 1999 the MOSIS changed the design rules for BiCMOS AMI technology from 1.2 to 1.5 microns according AMI recommendation. This change made to improve stability of the process parameters. So we have to change layout of CMP16_E to suit new rules.
The new chip has name CMP16_F. Simplified schematic of this chip presented in Fig.1. Full set of schemes for this design also available.
Actual die size of the chip a little bit bigger that previous one, but it still suites to the same package (QFP 80).
The chip layout is presented in Fig.2.
The CMP16_F chip is submitted to MOSIS January 15 and will be back in March 25 (according the MOSIS schedule). 90 chips were ordered. That is enough for 3 chambers and some number of chips we hope to test under proton beam.
If the result of this submission will be perfect, we will ready for mass production, after the Rad. Hard test.
Del16 delay chip status
The 16 channel delay chip was designed to provide a compact
LVDS to CMOS level converter and a controllable delay circuit for anode signals. As far as the anode pulse arriving time must be aligned with accuracy 2-3ns, this delay circuit may not be very precise, but must be low consuming and easy controlled.
Schematic of this circuit was tested in previous submission to AMI1.2 microns technology via the MOSIS. The chip name is DEL8. This chip was tested and results were pretty good.
The delay channel structure is presented in Fig.3.
In this chip was implemented a serial interface to control delay.
This interface consists of a four bits shift register.
It is possible connect this shift registers in a daisy chain.
Interface schematic presented in Fig. 4.
New chip was designed for AMI 0.5 microns.
Layout of this chip is in Fig.5.
Chip specification (calculated figures)
Chip delay minimum - 20ns
maximum - 52ns
Delay step- 2ns -This figure adjustable “on board” by setting
“Pulse delay” current (Id)
Delay steps- 15
Delay code - 4 bit
Output pulse width 20ns – 100ns Adjustable “on board” by setting
“Pulse width” current (Iw)
Control interface signals
Reset (CLRB)– set all registers to zero, minimum delay.
Chip select bar (CHSB) select chip to download data
Clock (CLK)
Data Input (DIN)
Data Out (DOUT)
Chip submitted to the MOSIS for production January 21 and will be back March 30 (according the MOSIS schedule).
Anode front-end electronics integration issue
Board fixation.
Each AD16 board is directly connected to a protection board of a chamber. Special slots are made in the anode side cover of the chamber.
Size of the slot is fixed. Two holes for “grounding” screw will be drilled near each slot. A special cover box designed for the boards. This box will mechanically protect the boards, support the boards and make electrical shield for the boards. So this board must be pretty strong and well connected to the chamber cover. The construction of the box and the slots and other holes on chamber was discussed and a solution was agreed.
To insure that everything okay, a simple mock-up will be made in Fermilab.
We think that the latches on the protection board connector are not needed.
AD16 ALCT cabling
We assume that every cable may have its own length. But in real it will be a set of cables with a few lengths. Every cable must have a strain relief on the AD16 side as well as on ALCT side. There is a proposal for these devices.
How cables must be arranged on the top of a chambers is still under discussion.
AD16 boards cooling.
I am pretty sure that for the most chambers we need not special cooling system for anode front-end electronics. But there are few places were AD16 boards are located pretty close. We are planning to perform special temperature measurement to get an answer for cooling these places.
Radiation test.
As far as a CEU effect most significant we would like to joint
to all activities in this direction.
AD16 board very good suits to this test. There is only one chip on this board. Power regulator on board may be disabled, or even tested separately.
We would like to discuss and prepare all special equipment for monitoring power current.