2.2 Primary Memory
- Memory contents can represent either programs instructions or programs data.
Memory Organization
- Memory is built from millions of storage cells .
- Storage cells are organized into groups of n-bit which can be stored or retrieved in a single memory access each group is called word,
- Word size is processor dependent. It can be 8, 16, 32, 64-bit.
- Each word is assigned a location number called the word address.
- If address is given to individual words then the memory is word-addressable. However, if the address is given to individual bytes then the memory is byte-addressable. In this case, the word address is the address of the first byte in the word.
For example assume that a memory has a word of size 32-bit (4 bytes) then Figure
2.10 (a) shows the word addresses in case the memory is word-addressable and Figure 2.10 (b) shows the word addresses in case the memory is byte-addressable.
Figure 2.10: a) Word-Addressable B) Byte-Addressable
Memory Size
The memory size represents the total number of bits the memory can store. The size can be given in terms of K = (210) or M = 220 or G=230. There are many ways to interpret the memory size for example, if the total memory size is 96-bit, then it can be interpreted as: 96 memory words each of size one bit or 1 memory words each of size 96 bits or 8 memory words each of size 12 bits or 16 memory words each of size 6 bits. To have a full knowledge about the memory the size is always expressed as product of the number of words and the size of each word in bits.
Memory total size (bits) = #of words x size of each word in bits.
Memory Chip
Any memory chip has three sets of pins or connectors that are used to connect the memory to the outside world. These sets are:
1- Address Pins
2- Data Pins
3- Control Pins
If the memory is word-addressable and there are a total of 2K memory words, then the number of address pins is (K). Similarly, if the memory is byte-addressable and there is are 2K bytes, then the number of address pins is (K). Address lines are unidirectional.
The number of data pins is equal to the size of the memory word in bits. Data lines are bi-directional.
Control lines are Read control, Write control, and the chip enable control.
Figure 2.11: Different memory lines for 512Kx8 memory
Communication between the main memory and the CPU
Figure 2.12: Connection of the memory to the processor
The memory is connected to the processor by the address, data, and control lines as shown in the above figure.
Address lines at the processor side are connected to the MAR which has the same size as the number of address lines (Pins). Data lines at the processor side are connected to the MDR register which has the same size as the memory word.
Read and write Operations
Read operation steps:
- The processor loads the address of the memory word to be retrieved into MAR register.
- The processor will set the read control to 1
- The memory will respond by putting the content of the specified word into the data lines. This means that the word is now loaded into the CPU MDR register.
Write operation steps:
- The processor loads the address of the memory word to be written into MAR register.
- The processor will load the word to be written into MDR.
- The processor will set the write control to 1
- The memory will respond by storing the word at the specified address.
RAMs & ROMS
All the memories listed in the following table are considered to be random access which means that individual memory words can be accessed directly by specifying their addresses. However, for the main memory which is also called RAM words can be read and written easily and quickly. Also, main memory (RAM) is volatile. This means that there should be constant power supply otherwise if the power is interrupted then the data are lost. Thus, RAM can be used as temporary storage.
Table 2.1: Memory Types
There are two main types of RAM: Dynamic RAM (DRAM) and Static RAM (SRAM).
The following table shows the difference between both types:
Static RAM (SRAM) / Dynamic RAM (DRAM)Volatile / Volatile
Storage cell is a single Flip Flop which is built from six transistorsè Large storage cell / Storage cell is made of a single transistor and a capacitor è smaller storage cell
Contents are saved as long as the power is kept on. / Contents must be refreshed (reloaded) every few milliseconds to prevent lose.
Fast because no refreshing / Slow because of the refreshing
Used for cache / Used for main memory
Table 2.2: Comparison between SRAM and DRAM
Advanced DRAM types
- Synchronous DRAM (SDRAM): This type of RAM is controlled by the system clock which means that the CPU will know exactly when the memory will respond so the CPU can perform other tasks until the memory respond. In normal DRAM, CPU has to wait and stay idle until the RAM finishes and responds.
- Double data rate synchronous DRAM (DDR SDRAM): the same as SDRAM except that data output is provided on both the negative and the positive clock edges. In normal SDRAM, data is provided once per clock cycle.
- Rambus DRAM
This memory is not open standard like DDR SDRAM. It is developed by company called Rambus Inc. It is a proprietary technology that provides very high memory access rates using a narrow bus. This memory is adopted by Intel for Pentium & Itanium processors and it is the main competitor to SDRAM technology.
Read Only Memory (ROM) types
Read Only memory (ROM) contains a data that can not be changes. A ROM is nonvolatile; that is , no power source is required to keep the stored data. It is possible to read the ROM but not possible to write new data into it. ROM is used in many applications like to store the interpreter inside the CPU, and to store the program the will load the operating system when the computer is turned on. Also, ROM is used in embedded systems. Data are written into ROM when it is manufactured.
Programmable read only memory (PROM): is similar to ROM except that it can be programmed once in the field. The programming is done electrically by special equipment.
Erasable Programmable read only memory (EPROM): This type is called read-mostly memory. This type of PROM allows the stored data to be erased and new data to be loaded. It can be read or written electrically. However, before a write operation, all the storage cells must be erased by exposure of the chip to ultraviolet radiation through a window that is designed into the memory chip. The erasure process can be done several times. Each erasure can take as much as 20 minutes to perform.
Electrically Erasable Programmable read only memory (EEPROM): This type is called read-mostly memory. This type can be written into at any time without erasing prior contents. EEPROM can be erased by applying pulses to it instead of requiring it to removed and put into a special device for exposure to ultraviolet light. EEOROM is byte erasable which means only a single byte can be updated at a time. This makes the write operation takes considerably longer than the read operation.
Flash memory: It is intermediate between EPROM and EEPROM in both cost and functionality. Like EEPROM and unlike EPROM, flash memory uses electrical erasing technology. However, unlike EEPROM and EPROM, flash memory is block erasable and rewriteable. The whole flash memory can be erased in one or few seconds in addition it is possible to erase just blocks of memory.
Byte-Ordering
There are two systems for storing bytes representing numbers in memory words: little-endian and big-endian.
Little-endian: Bytes representing numbers are stored starting from the rightmost byte or the least significant byte then remaining bytes in increasing order of significance. This system is used in Intel processors and VAX machines.
Big-endian: Bytes representing numbers are stored starting from the leftmost byte or the Most significant byte then remaining bytes in decreasing order of significance. This system is used in SUN SPARC processors, IBM mainframes, Apple Mac, and most RISC machines.
Both systems stores ASCII codes of characters representing strings left-to-right.
The PowerPC is a bi-endian processor. It supports both big-endian and Little-endian modes.
Internet is Big-endian
Chapter 2 2 Dr. Fakhry Khellah - 2008 CS251