CSCI 235 Digital Circuit Design
Laboratory Exercise 9 – Simple Clock
Simple Clock
This circuit will display the seconds portion of a digital clock. The clock will count from 00 to 59, then start over.
Two seven-segment displays will be used to display the numbers.
A 7447 seven-segment display decoder/driver will be used to drive each display.
The counting function will be performed using 74191 synchronous up/down binary counters.
Pin Descriptions:
QA, QB, QC, and QD – These are the counter outputs. QA is the least significant bit.
A, B, C, and D – These are the load inputs. The outputs take on these values whenever the LOAD pin goes low.
CTEN – Count Enable. This pin has to be low for the counter to count. Bring it high to pause the counter.
D/U – Down/Up When this pin is low, the counter counts in ascending order (i.e. 1, 2, 3...). When the pin is low, the counter counts down.
CLK – This is the clock input. All inputs change simultaneously on the rising edge of the signal.
RCO – Ripple Clock Output. This output goes low when the count rolls over in either direction.
MAX/MIN – This output goes high when the count rolls over in either direction.
LOAD – When the load input is low, the clock is ignored and the counter outputs take on the load inputs. The load is asynchronous, meaning it does not wait for the next rising edge of the clock pulse.
Part 1
Connect a counter to a seven segment display. Drive the counter clock input with a button. The counter should cycle through 16 states.
Part 2
Design a decoder that detects the first invalid state (10), and loads 0 into the counter. The clock should now cycle through 10 states (0 through 9).
Part 3
Drive the clock with a 555 timer IC.
Part 4
Design a second counting stage that counts tens of seconds from 0 to 5. Drive the clock for this counter using the first circuit. You could use the first counter's decoder circuit, RCO output, or MAX/MIN output.