Readout Electronics R&D

ROelectronics3.doc 2:25 PM01/11/01

Readout electronics R&D

Introduction

Early R&D for the readout electronics are motivated by the many factors. Power consumption, heat rejection, and physical volume are needed inputs to the spacecraft design. Conventional implementations with discrete parts have been surveyed and will exceed any reasonable satellite power budget. Custom integrated circuits (ASICs) can reduce system power but their need to be moderately radiation tolerant requires a more complex design. The readout electronics implementation will be requirements driven and this is the first R&D activity. Following the acceptance of the requirements, effort will go into a conceptual design and partitioning of that design among ASICs and conventional parts. Several design and fabricate cycles will follow. We consider the proof of a viable, power optimized readout system to be a high-risk area, especially the development of radiation tolerant circuits, and that a prototype system needs to be developed during the R&D cycle.

The R&D tasks described below are

·  Develop requirements.

·  Develop conceptual design.

·  Develop system components.

·  Perform system testing.

·  CD1 planning.

Background information

The SNAP satellite will use scientific grade CCD’s and other pixel technologies in three instruments. All CCD and HgCdTe devices can be controlled and digitized with a common, modestly flexible electronics system. We have set the goal for ourselves that any new controller technology will be compatible with all the pixel technologies used in SNAP. Conventional CCD controllers are quite bulky and, more importantly, power hungry. Scaling up to the SNAP imager would require a power consumption of 1200 W, more than can be provided by the satellite power system. We have undertaken a program to specify a system implementation that includes IC’s to provide lower power consumption and dramatic reduction in parts count.

A series of attached figures show a concept for the CCD electronics chain: SNAP CCD (Figure 1), the cable driver and temperature monitor located on back of each CCD (Figure 2), and a block diagram of the remote electronics (Figure 3). We have begun the process of specifying the requirements for the CCD controller system. The major blocks per CCD are: 1) DC voltage generation, 2)clock generation, 3) correlated double sampler, 4) analog to digital converter, 5) temperature monitoring, 6) interface to instrument configuration bus, and 7)interface to image data buffer. While the overall architecture and requirements are far from complete, we feel that certain components can be well defined at this time.

Detector signal characteristics

The output characteristics of several manufacturer’s CCD’s are shown in Table 1. A small number (4 –16) of the Rockwell HgCdTe devices will be used.

Table 1. Sample characteristics of CCD and HgCdTe devices used in astronomical instruments

Manufacturer / Model /

Gain

/ Well depth / Read noise / Linearity / Polarity
mV/e / ke / e / %
LBNL / 3.5 / 130 / 4.3 / ? / positive
LBNL / SNAP / 6.0 / 130 / 3.7(2.5) / ? / positive
SITe / SI-424A / 1.0 – 1.3 / 150 – 200 / 5 – 7 / <1 / negative
EEV / CCD44-82 / 4.5 – 6.0 / 200 / 2.5 / ±0.5 / negative
Rockwell
HgCdTe / Hawaii 2 / 2 3 – 6.0 / 100 / <10
<3 (Fowler) / <1 / negative

The output structure of a CCD is shown in Figure 4. A floating diffusion capacitor is reset to a reference level before each pixel is readout. The reset voltage level is uncertain by the kTC noise of the reset transistor. The pixel charge is then transferred onto the capacitor and added to the uncertain reset level. The correlated double sampler (CDS) technique is used to remove the reset level; a sample of output signal after reset is subtracted from the output generated after the pixel charge transfer. This can be done digitally or analog. For an LBNL CCD, the post-CDS read noise can be as low as 2 e (Figure 5) using a dual-slope integration CDS. The sensitivity for the low noise CCD is 6 mV/e. The read noise is a function of the pixel read rate. The requirement for SNAP is to read a CCD in 20 seconds, corresponding to a 100 kHz pixel rate, corresponding to 5ms in the Figure 5.

The well depth of a pixel is the amount of charge than can integrated before blooming into adjacent pixels. For SNAP, the CCD well depth will be of order 120 ke and typical linearities are sub-1%. The range of signal levels of interest is from the noise floor to full well, 12 mV to 720 mV.

CCDs require several clocks to move the pixel charge around. A set of clocks performs a parallel shift of pixel columns into a serial shift register. The voltage swings of the clocks are approximately 10 V, the parallel clock capacitances are ~20 nF, and the serial clock capacitances are ~10 pF. The drain voltages for the output FETs are 20-25 V and the depletion voltage is 30-80 V. These are challenging voltage levels to generate and control in custom integrated circuits.

For HgCdTe devices, the reset and signal sample times are temporally disjoint and CDS is done digitally. The pixels can be non-destructively read. For example, the pixels are reset, the reset levels are digitized and stored, and after an exposure period the pixels are digitized again. A digital subtraction of the two arrays accomplishes the CDS function. Other noise reduction techniques, multiple Fowler sampling and up-the-ramp sampling are also done in the digital domain. Multiple Fowler sampling does many consecutive reads after reset and after exposure to statistically reduce the read noise. Up-the-ramp sampling makes periodic, continuous reads of the pixels during the exposure. This also reduces the impact of read noise and can detect cosmic ray charge deposition. The readout clocks for these devices are CMOS logic levels and the maximum output signal is less than 1 V.

Develop requirements

The operating characteristics of a variety of CCDs and HgCdTe devices have been surveyed and it is possible to establish requirements for an electronics readout system that is compatible with all of them. It is a goal for the SNAP electronics that it be uniformly implemented across all the instruments. The requirements document will address the following items:

·  On-detector electronics.

·  Correlated double sampler.

·  DC voltages and their cycling.

·  Clock parameters such as levels and shapes.

·  Clock sequencer and modes of operation.

·  ADC interface.

·  Data processor/memory interface.

·  Local resource configuration and control.

·  Overall power and control.

Progress has already been made in assembling materials for this document and it will be completed in March 2001.

Develop conceptual design

After agreement to the requirements document the system architecture will be developed including a block diagram. A good deal of engineering time will be spent on this high level design to make trades between ASIC and conventional parts implementations. At the moment, we speculate that two ASICs will be required, one to perform the precision analog processing of the correlated double sampling function and another to perform some part of the clock waveform generation. Other system level control and interfacing functions might be subsumed in the later ASIC.

System partitioning will be complete June 2001 and materials will be available for the ZDR the following month.

Development system components

After the completion of the system block diagram and the engineering decision about how each functional block is to be implemented, technology selection, design, fabrication, and test of the ASICs and conventional electronics can be begin.

The use of ASICs is motivated by at least three important concerns: 1) power consumption, 2) size and weight of the whole system, and 3) reliability.

As experienced in High Energy Physics instrumentation, the use of ASICs for readout of a large number of detector channels can reduce the size of the front-end electronics and the needed power. Many analog and digital components such as operational amplifiers, switches, power buffers can be merged into two or three ASICs. Large standing currents to load and unload highly capacitive interconnect media such as copper tracks or wire bonds on hybrids or printed circuit boards can be reduced and power saved. As an order of magnitude, the stray capacitance to ground of an interconnect between two chips a distance one centimeter apart on a multi-layer PCB is of the order of 1 pF. This is to be compared to 10 fF for a one-millimeter interconnect on an ASIC. As another example, the CFHT MegaCam front-end electronics built with discrete components dissipates 7.5 W per CCD, to be compared to 0.50 W as planned using ASICs.

Several functions have been identified that might particularly benefit from their integration as ASICs:

·  Correlated Double Sampling (CDS) that amplifies and filters the CCD analog output.

·  DC biases and clock waveform generation for the CCDs and HgCdTe sensors.

·  Control and interface to the data acquisition system.

Depending on the IC processes selected, functions could even be merged, as for example the CDS and ADC interface, or split, as the CCD control voltages generation and their buffering to the CCD.

All the electronics components must survive a lifetime radiation dose of 10 kRad at ~109 MeV/cm2. The number of IC processes available is therefore limited. Design kits should provide reliable semi-conductor devices models after irradiation. As well, the test plans will incorporate tests after irradiation.

Develop CDS ASIC

The correlated double sampler was identified more than a year ago as an item that would benefit for an ASIC implementation to reduce power and parts count and to meet the stringent analog processing requirements. A requirements document for this sub-component was completed in September 2000 and a design started for the DMILL radiation hard process that we access through a European multi-project organization. The design was submitted at the end of November 2000 and will return in four to six months. After test and revision, we plan on a second submission of this chip

A second technology will be selected as a backup. Two candidates have been identified and a decision will be made early 2001. An important consideration in selecting among available processes is the maximum usable voltage that impacts the achievable dynamic range. At the other end, thermal and 1/fn noise have to be kept small compared to the CCD readout. The availability of reliable noise models will also be a determining selection factor. A second iteration of this design is also scheduled.

As described above, we are pursuing two technologies through two design iterations for this component. Low noise performance and radiation tolerance are absolutely critical for extracting the most information from the CCDs and HgCdTe devices.

Develop clock/bias/control ASIC

As stated above, we presently think that some fraction of the clock generation will need to be implemented in an ASIC or two. Additional functions such as bias voltage generation and control and digital interfacing to the data acquisition system might also be incorporated. The final solution might be a single chip or two chips, a pure digital control chip and a power buffer in a high voltage process. Some control functions and interfaces to the data acquisition system might also be integrated. This will be determined during the system conceptual design phase. Candidate IC processes are listed in Table 2.

After selecting an appropriate semiconductor technology, two cycles of design, fabrication, and test have been scheduled. The first cycle completes in February 2002.

Table 2

DMILL / Harris-Intersil
UHF2 / Harris-Intersil
RSG / Peregrine / TSMC
Gate length (mm) / 0.8 / 0.6 / 0.5 / 0.25
Voltage (V) / 5.0 / 6.0 / 40.0 / 3.3 / 2.5V
Rad. Tolerance / 10 Mrad / 300 krad / 300 krad / 100 krad / 50 Mrad
Turn-around (Wks) / 25 / 18 / 14 / 8-10 / 16
Cost ($/mm2) / 10 / 10 / 27 / 38

Develop commercial parts

To be able to test the ASICs and to instrument the Gigacam demonstration unit several parts of the readout system that will probably use conventional technologies need to be designed and built.

Co-located with the CCD will be electronics to buffer the CCD source follower FET, drive the cable to the remoted readout electronics, and to filter DC voltages. Radiation tolerant components need to be selected and a printed circuit board designed and fabricated.

The CCDs will be connected to the readout electronics with some sort of cable. A constraint on the design is that the cable conduct very little heat into the 150K environment of the CCDs from the readout electronics operating at essentially room temperature. Present thinking is that this will be a flex circuit using a low conductivity metal alloy.

There will inevitably be some amount of commodity parts surrounding the ASICs on the readout cards. These will have to be selected to meet space environment requirements. One component in particular that we think can be a commercial part is the ADC. A survey of commercial parts will be undertaken, one or two parts selected, and a program to certify them for space flight will be performed, either in-house or commercially.

All these components need to be tested and available to readout the Gigacam demonstration unit.

Perform system testing

Beginning in August 2002, all the components developed above will be brought together to perform a system test. This will then be connected to the CCDs in the Gigacam demonstration unit, hopefully with results available at the time of CD1.