EE 141 Fall 1999

Homework Set #9

Due Wed. Nov 24 1999, 5.00 pm

Problem 1)

a) Design a circuit to implement the truth table shown below. A gate level design is sufficient

S / R / Q / Q’
0 / 1 / 1 / 0
1 / 0 / 0 / 1
1 / 1 / Q / Q’

b) The circuit you have designed above is embedded in the larger circuit shown below. Complete the timing diagram for the output



Problem 2)

Do problem 3 from Chapter 6 of the textbook.

Problem 3)

Consider the monostable multivibrator circuit drawn below. Calculate the output pulse width.

Vt(dep) = -0.5V

Vt = 0.4 V

K’ = 100A/V2

 = 0

Assume Vin has been 0 for sometime and then suddenly switches to 2.4V. How wide is the pulse at the output (i.e. how long is Vout high)? Assume that the output switches when the voltage on the gate input to the driver crosses 1.2 V. Initially the output is low, so the driver is on. Then when Vin goes high, the driver turns of. Assume that the driver turns on again when its gate input voltage reaches 1.2V.


Problem 4)

Circuit on the following page is a pseudo-NMOS Schmitt trigger. Assume that the PMOS transistor remains in saturation over entire range of operation. (W/L)1 = 3/2.5 and (W/L)2,3,4 = 30/2.5. Vdd = 1.5V, Vtn = Vtp = 0.4V, kn =115A/V2 kp=-30A/V2

a)Compute VOH and VOL

b)Compute the switching points VM+ (for input making low-to-high transition) and VM- (for the input making a high-to-low transition).

c)Draw the VTC. Compare results with SPICE simulations. In particular, you should obtain different VTC curves for high-to-low transitions and low-to-high transitions.

d)Perform a transient analysis with the following as input:-

Vtest vin 0 PWL 0 0 50n 0 100 Vdd 150 Vdd 200 0

Problem 5)

Consider the following simple processor, consisting of a pipelined data path and a finite-state machine based controller. RF, PR, and IR denote edge-triggered flip-flops, while DP1, DP2, and FSM denote logic modules. Minimum and maximum delays of the modules are shown in the table next to the Figure. You may ignore the delay of the interconnect as well as the delays of the registers. The ’s at the clock inputs of the registers denote the absolute skew between the clock source and the register.

Min Delay / Max Delay
DP1 / 3 / 10
DP2 / 2 / 8
FSM / 1 / 5

a)Write down the necessary constraints on the clock skews to avoid race conditions.

b)Derive the constraints on the clock period in the presence of skew.

c)Determine minimum possible clock period.

d)Determine the values of the skews for which this minimum period is achieved.

e)Propose a revised architecture that would reduce the clock period (changing circuit style is not an option). Explain your design, and discuss the disadvantages of your approach.