ADVANCED PACKAGING
Advanced packaging is an enabling technology providing solutions for the semiconductor market down to below the 10 nm process node. These packages show a strong growth rate.Packaging technologies continue to evolve to meet the requirements needed in applications ranging from high-performance computing and communication to mobile electronics.
Observations related to mobile products include:
· New package form factors to satisfy high-performance, high-bandwidth, and low power consumption requirements in a thinner and smaller package
· Packaging solutions to deliver systems-in-package (SiP) capabilities while satisfying low-cost requirements
· Shorter lifetimes and differing reliability requirements. For example, high-end smartphones and tablets, the key high reliability requirement is to pass the drop test; and packaging material solutions are essential to delivering such reliability.
Packaging must provide a low-cost solution and have an infrastructure in place to meet steep ramps in electronic production.The move towards bumping and flip chip has only accelerated with the growth in mobile electronics, though leadframe and wirebond technologies remain as important low-cost alternatives for many devices. Wafer-level packaging has seen strong growth, especially in mobile devices, because it provides a low-profile package. As companies move to the next semiconductor technology node, smaller die are possible, allowing a greater number of die per wafer. At the same time, the number of I/Os continue to increase, routing them requires with small diameter solder balls with fine pitch or a new technology to fan-out the I/Os. With concerns of board level reliability at <0.3mm pitch, many companies have chosen to adopt FO-WLP. In the case of application processors, the use of a FO-WLP without a substrate provides better electrical performance than the current flip chip chip-scale package (CSP). The absence of a substrate also provides a direct thermal path to the board and measurements at the board level indicate it has better thermal performance. While stacking the application processor and memory with through silicon vias (TSVs) would provide the ultimate in low profile and electrical performance, ther business issues of coupling logic and memory and the lack of adequate thermal solutions continue to push this technology out. FO-WLP is a disruptive technology because there is no substrate and thin-film metallization is used for the substrate. The use of redistribution layers patterned with semiconductor processing technology allows the fabrication of finer feature sizes (<5 µm lines and spaces).
Packaging requirements for the wearable and IoT markets vary depending on the application, the end use environment, and reliability needs. Thin and small are a must though like other applications cost versus performance will determine what package type is adopted for a given wearable product. Cost will become a major issue as we move into the IoT era. In many of these applications, as well as mobile phones, increased use of SiP is common. In today’s world of mobile product introductions that must ramp in four to five months and may only have a lifetime of a year, SiP is essential to the success of new products in this space. SiP is defined as two or more dissimilar die, typically combined with other components such as passives, filters, MEMS, sensors, and antennas, assembled into a standard footprint package to created a functional system or subsystem. Designing a system-on-chip (SoC) solution in many cases is too costly and takes too long. Drivers can differ slightly depending on the application. In the wireless market, the drivers are integration, form factor, cost, and shielding. Time-to-market is critical.
Market demand for smaller, smarter, and faster devices with lower power dissipation is driving the development of new architectures to meet the needs of system users. Bandwidth demands and device latency issues, coupled with power management, delivery and distribution needs, have created drivers for a new integrated circuit (IC) architecture solution. Many semiconductor industry activities point to the adoption of though silicon via (TSV) technology as a method to achieve interconnect density in the third dimension and as a replacement for the long interconnections found in current planar structures. Silicon interposers are being used in graphics, networking, and possibly server applications. Memory stacks with TSVs are in production for these high performance applications. While the volumes are not high compared to mobile phones, the value for unit is significant.
Click here to download Advanced Packaging presentation
For more information about trends and applications related to advanced packaging, visit www.techsearchinc.com.