PCI-X CORE

Product Description 1.0

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Features

·  Complies with PCI-X Addendum to the PCI Local Bus specification rev 1.0a

·  Supports 32/64-bit PCI-X Initiator/Target Interface

·  Supports Bus Speeds up to 100 MHz

·  Type0 Configuration header supported. Up to Six Base Address Registers (BAR) and expansion ROM registers

·  Supports all the command and status Registers

·  Supports user defined Configuration Registers

·  Supports 64-bit addressing

·  Supports all memory and I/O commands.

·  Supported PCI-X functions

- I/O Read

- I/O Write

- Configuration Read

- Configuration Write

- Memory Write

- Memory Write Block

- Memory Read Block

- Memory Read DWORD

- Split Completion

·  Wait state insertion supported and can generate all types of terminations

·  Parity generation and checking. Generates System errors and Parity errors

·  Fully synthesizable Verilog RTL source code

·  Fully functional Verilog test-bench

·  Full synthesis support with synthesis scripts and constraint files for Synplicity

PCI-X Core Facts
Implementation details
CLBs Used / 20%
IOBs Used / 30%
Device Type / XC2V250 FG456
Operating Frequency / 100 MHz
Provided with Core
Documentation / Core Documentation
Design File Formats / Verilog Source code
Synthesis Scripts
Verification Tool / Verilog-XL
Test Bench / Verilog Test Bench
Design Tool Requirements
Xilinx Core Tools / M1 5.1i
Entry/Verification Tools / Verilog XL
Synthesis Tools / Synplify Pro v 7.0
Support
Support provided by Comit Systems, Inc.

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Fig 1 Block diagram of PCI-X Core

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Functional Description

The PCI-X core supports PCI-X bus protocol, which can be operated at maximum frequency of 100 MHz. The PCI-X core architecture allows it to be connected as 32-bit or 64-bit device. Support for dual address cycles (DAC) is provided. The PCI-X core can be partitioned into four major blocks as shown in Fig 1.

PCI-X Target State machine

The target state machine supports all DWORD, memory and configuration transactions.

Configuration transactions are always 32-bit transactions and the state machine informs the User Logic Interface (ULI) of the transaction progress and command. This block asserts the required control signals, provides data in the case of the write and receives data for read transaction.

Memory transactions can be single or burst (32/64-bit). The PCI-X core supports wait state insertion for burst read/write. In a read transaction data is transferred from the ULI side to the PCI-X Target. In a write transaction data is transferred from the PCI-X Target to the ULI along with the necessary control signals. The ULI can generate all type of terminations.

(Retry, Data transfer, Split, Disconnect_next_ADB, Single phase disconnect and Target Abort)

I/O transactions are always 32-bit transactions. Any of the six Base Address Registers can be configured to reserve I/O space. Like memory transactions, the ULI can generate all types of transactions.

(Retry, Data transfer, Split, Disconnect_next_ADB, Single phase disconnect and Target Abort)

PCI-X Initiator State machine

The initiator state machine supports all DWORD, and memory transactions.

The ULI requests the Initiator state machine for 32/64-bit transaction. The PCI-X master asserts the external request to the PCI-X bus arbiter for bus ownership. When the PCI-X bus arbiter grants bus ownership by asserting the grant signal, the ULI is alerted and must provide the address and command with necessary control signals.

The ULI can generate all kind of Initiator terminations. Target terminations are informed to the ULI with the proper target response to enable the ULI side to take the necessary actions based on it.

PCI-X Configuration registers

The PCI-X Core configuration space has 64 bytes of Type0 Configuration header, 64 bytes of PCI-X capabilities registers and user defined registers.

This includes six Base address registers, Command, Status and capabilities list required for PCI-X.

Address Decoding

The PCI-X Core supports full 64-bit addressing and handles dual address cycle. When an address is broadcast on the bus, the decode module compares it to the base address registers for a match. If one occurs, the target state machine informs the ULI of the transaction with the appropriate address/command and control signals.

Parity Control

The Parity error generation and checking is done for both Master and Target Interfaces. System error is generated Address and Attribute parity errors and the appropriate status registers set. The ULI can terminate the transaction with a Target abort or Master abort for address and attribute parity errors. Data parity errors are generated and checked for both write and read transactions.

Ordering Information

Enquiries for this product may be directed to:


Comit Systems, Inc.

3375 Scott Blvd. Ste 139

Santa Clara, CA 95054, USA.

Phone: +1 (408) 988-2988

URL: http://www.comit.com

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