Power and energy efficient architectures

Introduction:

Microprocessors have conventionally been designed to yield maximum performance. Different design approaches have been taken and implementation technologies.

In the drive for improved performance through higher integration little attention has been paid to power consumption. This thesis shows how architectural features and performance

Can be traded against power consumption to improve the performance-energy efficiency. Energy efficient fetch design that still achieves performance is important because overall chip energy consumption may limit not only what can be integrated onto a chip.

The challenging trends, systems have consistently delivered higher performance as well as greater energy

Efficiency over generations. The increased complexity in multi-core architectures. With the current technology trends it is increasingly challenging to stay within power envelopes without careful planningand optimization.

Multi-Component Cache relatedenergyefficiency:

Cache has the same tag component arrangement as a regular set-associative instruction cache, but rather than

a single set-associative data component, there are a number of direct mapped data components.

Cache lines should be long, although no line size can be identified as optimal; 64 bytes per. Line appears to be a good compromise. Again, the tables show that the line sizes should be shorter when optimizing for energy efficiency rather than for performance.

The continuous drive for higher levels of performance has pushed total power envelope. However, processors have become more efficient, being able to accomplish more work with the same power budget.

Performance and Analysis:

Power/performance analysis is an integral part of early-stage definition of microprocessors. In general, power-performance modeling and validation methodology is a key investment that will prevent post-silicon surprises. In addition, early stage analysis eliminates fundamental design decision errors that can lead to post-silicon power overruns and performance shortfalls. Furthermore, power analysis and tuning must percolate through all stages of design with closed loop feedback to higher levels.

Summary:

A collection performance in next generation microprocessor architectures will be constrained by power dissipation more than any other design criteria. As a result, static and dynamic co-optimization of power performance characteristics are both essential in achieving green processing.

Using an casting communication Paradigm in clustered node architecture in an optical network, we show a decrease in the energy Consumption.

Temporal Behavior of Three dimensional Multi-Core Architectures

Towards Run-Time Thermal Management. IT herm, 2010.

Result of the research:

  1. The processors high fetch bandwidth for wide
  1. Effective design that will scale to future processor technologies a complexity.
  1. perfecting to better tolerate memory latencies
  1. The power energy design that is as efficient as possible

Reference Paper:

  1. Energy Efficient Architectures for Optical Networks.
  1. High Performance and Energy Efficient Serial Prefetch Architecture.
  1. Trends and Techniques for Energy Efficient

Architectures.

The end

Advanced computer architecture

Power and energy efficient architectures

Name: Audai Sadeq Amer

Totter

Dr. Sulieman Bani-Ahmad