@head: Tensilica's latest and greatest configurable processor
@deck: New Xtensa 6 processor core provides fastest customization path, lower power, and advanced security provisions
@text: Ever since I first became aware as to what the chaps and chappesses at Tensilica (www.tensilica.com) were up to, I thought it was a mega-cool-concept.
Just to make sure we're all tap-dancing to the same set of drums, the idea is that they have a processor core called Xtensa that is a 32-bit post-RISC engine comprising around 25K gates with roughly the same performance as an ARM9.
Now let's assume that we have some application created in full ANSI standard C/C++. We start by running a special tool that analyzes our application and evaluates millions of possible processor extensions based on techniques like single-instruction-multiple-data (SIMD) and vector operations, operator fusion, and parallel execution. This tool then offers us a selection of configurations showing tradeoffs in terms of different architectures versus performance, gate counts, and power consumption.
Once we've selected the configuration that best satisfies our needs, we next run a special processor generator that customizes the Xtensa core with special extensions. This generator outputs the RTL for our custom core along with a custom compiler, assembler, instruction set simulator (ISS), and source-level debugger.
Finally, we use our new custom compiler to compile our original C/C++ application and generate the corresponding machine code that will be run on our custom processor. The result is an incredibly fast processor that often achieves the same throughput you'd expect if you created a dedicated hardware accelerator. Also of interest is the fact that our custom core will be incredibly power efficient, because the processor generator automatically implements extremely sophisticated clock-gating schemes.
Enter the Xtensa 6
As if all of the above wasn't enough, Tensilica recently announced a new version of its configurable and extensible Xtensa processor family – the Xtensa 6. This little scamp adds some enhancements as compared to its predecessor, including (a) approximately 25 to 30 percent lower power and (b) advanced security provisions in MMU-enabled configurations through a “no execute” bit that provides enhanced protection against malicious code.
Lower Power for Handheld Applications
With regard to power, Tensilica has significantly improved the base architecture of the Xtensa 6 processor, resulting in a 25-30 percent improvement in power dissipation. Several techniques were employed. Tensilica used both fine-grain clock gating, which turns off power to small sections of the processor when not in demand, and coarse-grain clock gating, which conserves power throughout much larger portions of the chip. For example, when a processor activity such as a cache-line fill occurs, coarse-grain clock gating is activated, saving valuable power.
Advanced Security Provisions
In this newest member of the Xtensa processor family, Tensilica employs advanced security provisions in the Xtensa MMU (Memory Management Unit) configuration option similar to what AMD and Intel have provided for personal computers. While AMD calls the feature Enhanced Virus Protection (EVP) and Intel calls it eXecute Disable (XD), it is generically known as NX for No eXecute. NX provides the ability to protect portions of memory so processor instructions can’t execute in those areas. In Xtensa 6 configurations that employ the full virtual memory capability of the Xtensa MMU, the new security features of the Xtensa 6 design set some areas of memory off bounds, thus helping to prevent worms and other types of malicious code from executing functions. This will be of especial interest to designers planning to run the embedded Linux operating system on Xtensa 6 processors, as this feature will be incorporated in future versions of the Linux operating system.
What can I say? I love this stuff! Until next time, have a good one!