Lecture 39
HDL Description of 16X8 SRAM
FIGURE A block diagram of 16X8 static memory.
VHDL 16×8 SRAM Description
library IEEE;
use IEEE.STD_LOGIC_1164.all;
--Build a package for an array
package array_pkg is
constant N : integer := 15;
--N+1 is the number of elements in the array.
constant M : integer := 7;
--M+1 is the number of bits of each element --of the array.
subtype wordN is std_logic_vector (M downto 0);
type strng is array (N downto 0) of wordN;
end array_pkg;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all; use work.array_pkg.all;
entity memory16x8 is
generic (N : integer := 15; M : integer := 7);
--N+1 is the number of words in the memory; M+1 is the --number of bits of each word.
Port (Memory : inout strng; CS : in std_logic;
ABUS : in unsigned (3 downto 0);
Data_in : in std_logic_vector (7 downto 0);
R_WRbar : in std_logic;
Data_out : out std_logic_vector (7 downto 0));
end memory16x8;
architecture SRAM of memory16x8 is
begin
com : process (CS, ABUS, Data_in, R_WRbar)
variable A : integer range 0 to 15;
begin
if (CS = '1') then
A := TO_INTEGER (ABUS);
-- TO_INTEGER is a built-in function
if (R_WRbar = '0') then
Memory (A) <= Data_in;
else
Data_out <= Memory(A);
end if;
else
Data_out <= "ZZZZZZZZ";
--The above statement describes high impedance.
end if;
end process com;
end SRAM;
Verilog 16×8 SRAM Description
module memory16x8 (CS, ABUS, Data_in, R_WRbar, Data_out);
input CS, R_WRbar;
input [3:0] ABUS;
input [7:0] Data_in;
output [7:0] Data_out;
reg [7:0] Data_out;
reg [7:0] Memory [0:15];
always @ (CS, ABUS, Data_in, R_WRbar)
begin
if (CS == 1'b1)
begin
if (R_WRbar == 1'b0)
begin
Memory [ABUS] = Data_in;
end else
Data_out = Memory [ABUS];
end
else
Data_out = 8'bZZZZZZZZ;
//The above statement describes high impedance
end
endmodule
endmodule
HDL description of Finite state Machine
FIGURE 7.7 State - diagram of a finite sequential - state machine.
VHDL State Machine Description
library IEEE;
use IEEE.STD_LOGIC_1164.all;
--First we write a package that includes type "states."
package types is
type op is (add, mul, divide, none);
type states is (state0, state1, state2, state3);
end;
-- Now we use the package to write the code for the state machine.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.types.all;
entity state_machine is
port (A, clk : in std_logic; pres_st : buffer states;
Z : out std_logic);
end state_machine;
architecture st_behavioral of state_machine is
begin
FM : process (clk, pres_st, A)
variable present : states := state0;
begin
if (clk = '1' and clk'event) then
case pres_st is
when state0 =>
if A ='1' then
present := state1;
Z <= '0';
else
present := state0;
Z <= '1';
end if;
when state1 =>
if A ='1' then
present := state2;
Z <= '0';
else
present := state3;
Z <= '0';
end if;
when state2 =>
if A ='1' then
present := state3;
Z <= '1';
else
present := state0;
Z <= '0';
end if;
when state3 =>
if A ='1' then
present := state0;
Z <= '0';
else
present := state2;
Z <= '0';
end if;
end case;
pres_st <= present;
end if;
end process FM;
end st_behavioral;
Verilog State Machine Description
`define state0 2'b00 `define state1 2'b01 `define state2 2'b10 `define state3 2'b11
module state_machine (A, clk, pres_st, Z);
input A, clk;
output [1:0] pres_st;
output Z;
reg Z;
reg [1:0] present;
reg [1:0] pres_st;
initial
begin
pres_st = 2'b00;
end
always @ (posedge clk)
begin
case (pres_st)
`state0 :
begin
if (A == 1)
begin
present = `state1;
Z = 1'b0;
end else
begin
present = `state0;
Z = 1'b1;
end
end
`state1 :
begin
if (A == 1)
begin
present = `state2;
Z = 1'b0;
end
else
begin
present = `state3;
Z = 1'b0;
end
end
`state2 :
begin
if (A == 1)
begin
present = `state3;
Z = 1'b1;
end
else
begin
present = `state0;
Z = 1'b0;
end
end
`state3 :
begin
if (A == 1)
begin
present = `state0;
Z = 1'b0;
end
else
begin
present = `state2;
Z = 1'b0;
end
end
endcase
pres_st = present;
end
endmodule
FIGURE Simulation waveform of the state machine