DDR1/DDR2 SDRAM Controller Core

Product description 1.01

Features

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Core facts
DDR1/DDR2 SDRAM Controller
Core specifics
Example Device / XC2V500*
CLBs used / ~388/768
Slices used / ~1552/3072
IOBs used / ~For 16 bit DDR AHB bus, 160/264
Operating Frequency / ~100MHz
Device Features used / DCM ( 2/8)
Provided with Core
Documentation / Core Documentation
Design File Formats / Verilog/VHDL Source code
Synthesis Scripts
Test Bench / Verilog Test Vectors
DDR-1/2 models for verification / Verilog models
Configuration file / Extracted from data sheet of DDR device to provide timing parameters for core
Design Tool Requirements
Xilinx Core Tools / P&R tool
Entry/Verification Tools / Cadence, ModelTech
Synthesis Tools / Synopsys DC, Synplify Pro.
Support
Support provided by Comit Systems
  • Supports memory devices from all major vendors
  • Supports up to 4Gb DDR1/DDR2 devices
  • Adheres to JEDEC standard
  • Generic Application bus interface
  • Supports multiple agents on application bus interface
  • Supports multiple inbuilt arbitration schemes (RR, Weighted RR) or user defined arbitration schemes or external arbitration
  • Supports DDR1/DDR2 devices with 4 banks or 8 banks
  • Programmable CAS latency for DDR1/DDR2
  • Programmable additive CAS latency implementation for DDR2 to optimize command bus utilization
  • Programmable timing parameters viz. tRCD, tRP, tMRD, tRFC, tRRD, tCCD, tRDL, tRAS, and twr
  • Programmable auto-refresh time interval
  • Configurable address mapping between application address bus and DDR row, column, bank addresses to suit to your applications bandwidth optimization
  • Configurable command queue depth to optimize the bank activation, pre-charge and data rate
  • Supports Power down and self refresh
  • DLL based DDR data (DQ/DQS) interface
  • On die termination Enable/disable support
  • Will support OCD calibration in DDR2
  • Generates manufacturer/device dependent timing parameter file for register programming

* Min. Xilinx Spartan 3 device: XC3S400

  • Available in Verilog/VHDL with extensive verification suite for functional, post-synthesis and post-layout verification
  • Can be customized for the following:
  • Various microprocessors bus or specific application bus interface
  • Various speed grades
  • Various FPGA/ASIC vendors
  • For any user application

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General Description


This DDR2 controller can be used for interfacing with DDR1 or DDR2 devices. All timings tRCD, tRP, tMRD, tRFC, tRRD, tCCD, tRDL, tRAS, and twr are programmable for compatibility with devices from different vendors at the operating frequency of the application. Address mapping between the application bus address and Row/Column/Bank is configurable, so that the controller can be optimized for your application. The controller is designed to have a command queue (depth is parameterized) to optimize the bank activation and pre-charge operations.The main blocks of controller are as follows:

  1. Application Interface
  2. Initialization block
  3. Refresh and Power down control block
  4. Command queue
  5. Command scheduler
  6. Transaction Handler
  7. DDR control interface
  8. Address path

Verification Methods

The DDR SDRAM Controller has been extensively tested using the test bench developed at Comit Systems. The test bench is also available with the core.

Comit Systems, Inc.

3375 Scott Blvd. Ste 139

Santa Clara, CA 95054, USA.

Phone: +1 (408) 988-2988

URL:
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