1BM1 / October 22nd, 2009 / F. J. Sànchez i Robert
- MI-2: 25 min. Grades will be available on October, 29th
- Questions about the exam: TU: 12 h – 14h; TU: 15 h – 17 h; TH: 11 h – 13 h
VERY IMPORTANT: Draw a general schematic or plan, develop the exercise and justify the results always explaining what are you doing
Minimum 2
1. Obtain the specifications (the truth table) of the circuit shown in Fig. 1. Apply the following analysis procedure which consists of 6 steps.
Fig. 1 Combinational circuit to be analysed: g = f(a, b, c)
a) Draw the circuit and plan a strategy using a concept map.
b) Do a gate analysis in order to obtain an algebraic expression.
c) Transform the algebraic expression to a simple SoP (or a PoS) using Boole Algebra.
d) Transform the SoP (or the PoS) to a sum of minterms (or a product of maxterms).
e) Fill in the truth table.
f) Verify your result using a circuit simulation.
2. Design an equivalent circuit for g = f(a, b, c) minimising by Karnaugh and using only NOR. Capture your schematic in Proteus and verify your implementation.
Fig. 2 Entity to be designed: g = f(a, b, c).
Direct verification using WolframAlpha
truth table (!a and b and !c) or ( (a and !b) and ( a or (!b xnor c) or ( (!a or !b) and !(a and !b) ) ) )
or in this other format:
truth table (!a b !c) || ( (a !b) & ( a || (!b xnor c) || ( (!a || !b) & !(a & !b) ) ) )
So, the g = f(a, b, c) = å (2, 4 ,5 )
logic circuit (!a & b & !c) || ( (a & !b) & ( a || (!b xnor c) || ( (!a || !b) & !(a & !b) ) ) )