Project GuideLiTH
Project Title
Sub-Title
Editor
Version 1.0
Status
Reviewed / Supervisor / Date reviewedApproved / Supervisor / Date approved
TSEK06 VLSI Design ProjectGroup XXLIPs
Documentation Responsible1
Project GuideLiTH
PROJECT IDENTITY
Project group nr, Year/Semester,
LinköpingUniversity, ISY, Electronic Devices
Name 1 / Customer relations (CUS) / Phone nr. /
Name 2 / Documentation responsible (DOC) / Phone nr. /
Name 3 / Design responsible (DES) / Phone nr. /
Name 4 / Test responsible (TST) / Phone nr. /
Name 5 / Implementation responsible (IMP) / Phone nr. /
Name 6 / Project leader (PL) / Phone nr. /
E-mail list for entire group: e-mail list for entire group
Webpage:address to group webpage
Customer:Customer description, 581 00 LINKÖPING,
phone to customer. 013-11 00 00, fax: 013-10 19 02, e-mail address
Customer contact person: name, phone, e-mail address
Course responsible: Atila Alvandpour,
Supervisor: name, phone, e-mail address
TSEK06 VLSI Design ProjectGroup XXLIPs
Documentation Responsible1
Project GuideLiTH
Create a table of contents here
How you create a table of contents:
Insert -> Reference -> Index and Tables …
(Formally; Tab leader: ……; Show levels: 3, Show page numbers: check; Right align page numbers: check)
-> OK
Table of Contents
Table of Contents......
1Introduction......
2Time Plan......
2.1Activities......
3References......
Documentation history
Version / Date / Changes made / Done by / ReviewedTSEK06 VLSI Design ProjectGroup XXLIPs
Documentation Responsible1
Check List for Tollgate 4 / Milestone 8LiTH
2018-09-15
1Introduction
Figure 11: Figure caption text
Figure text should always be used for figures and pictures.
Add figure text by righ clicking on the figure/picture and select Caption
Select label: Figure
Change the formatting style to Figure Caption
Table 11: Table caption text
A / B / CItem / 3 / 5 / 7
Table text describing all tables should always be used.
Add table caption by selecting the table and choosing:
Insert Reference Caption…
Select label: Table
Change the formatting style to TABLE CAPTION
2Time Plan
2.1Activities
In Table 61below are some of the activities that are recommended to have in the time plan for tollgate 1-3 (TSEK06).
Table 21: List of basic activities in the project.
Nr / Activities / Description1 / Time plan / Make time plan and keep it up to date
2 / Pre-study / Litterateur search, find good potential implementation structures.
3 / High level modeling / Create a high level model for a design that functions according to the specification
4 / Status report for TG1
5 / Transistor block design / Create schematics of all blocks and verify that they work according to specification.
6 / Chip designs on transistor level / Complete schematic of chip and verification
7 / Status report for TG2
8 / Block layout and verification / DRC, LVS, verification
9 / PAD frame / Layout and decide which pads to use, DRC and LVS.
10 / Chip core layout / Global place and route, DRC, LVS, verification.
11 / Generate fill and additional layers and Tape-Out
12 / Verification plan / Decide what should be measured and how.
13 / Project report
14 / Project presentation
3References
Write a reference list like the example below.
[1].Rabaey Jan M., Chandrakasan Anantha, and Nikolic Borivoje, Digital Integrated Circuits – A design perspective, Second edition, Prentice Hall, 2003, ISBN 0-13-120764-4.
TSEK06 VLSI Design ProjectGroup XXLIPs
Documentation Responsible1