Resume

Name: AVIRAL MITTAL

Date of Birth: 15 Nov 1974

Contact Information

29 Burnvale, Livingston

Scotland. EH54 6DD

Phone: +44-1506-442 426(Land Line), +44-7739286557(Mobile)

E-mail: ,

Web:

Objective

To become a key technical resource for an organisation/institution, where I am able to explore my full potential, add to my learning curve, as well as contribute effectively and efficiently to achieve organisational goals.

Education

MSc System Level Integration, University of Edinburgh(ongoing)

Grades obtained so far: First Term Grades.

Subject / Grade Awarded
Introduction to Embedded Software / A
Introduction to HDL / A
Embedded Software-I(DSP) / A
VLSI / A
IP Block Authoring / A

‘A’ is the highest grade awarded by University of Edinburgh in a subject.

B. Tech. (Bachelor of Technology) in Electronics Engineering, Institute of Engineering and Technology, Lucknow, India, ( a 4 year degree course(1994-1998)

Work Experience :Total Experience 7+ years. Worked with Philips Semiconductors UK, Texas Instruments UK, STMicroelectronics, India Noida.

About Me:

I am currently pursuing MSc at Institute of System Level Integration, ( Livingston, Scotland.

I would like to work in the following areas following my MSc.

DSP, Audio/Video compression/decompression Algorithms, Audio/Video Processing, Image processing Algorithms, Audio/Video Codecs, Ultra Low Power VLSI Architectures, Low power IP design and Development. DSP hardware design and implementation. SoC Design, Architecture.

Prior to joining MSc at ISLI, I had worked in the Semiconductor Industry with big multinationals like Texas Instruments UK, Philips Semiconductors UK and STMicroelectronics, India. The idea to quit job and pursue MSc is to be able to work in a area which best matches withboth, my interests and the interests of the organisation I would be working in.

Relocation: I am happy to re-locate to USA/Canada if the situation warrants it.I hold a B1 Visa for US travel valid until Nov 2014.

My professional Career till date:

INVENTIONS/PATENTS :

I invented the following two methods and filed patents for the same as a sole inventor, while working for Philips Semiconductors Southampton UK.

  • Invention and Design of Built In Interconnect Self Test Machine PCT/IB2004/001750
  • Invention and Design of Delay Fault Pulse Generator: PCT/IB2005/052900

IPs Developed:

  • ISO 11732-3 MP3 DECODER: I am nearing completion of a Low Power Hardware MP3 decoder IP. The design is done as a VHDL RTL, and the verification is based upon a reference C-model, which is also developed by myself. The target frequency is 5MHz, though I am researching upon 1-2MHz feasibility by using various architectural exploration techniques.A part of the reference C-Model can be downloaded from which serves as a Bit-Stream Parser, and lets the user understands mp3 bit stream format. More than 100 downloads have already been done from my site. The site is dedicated to this project.
  • CORDIC RTL:This RTL is a Synthesizeable CORE which calculates SIN, COS functions of a given angle. It is suitable for FPGA/ASIC implementation.
  • SDRAM Controller:JEDEC compatible SDRAM Controller RTL suitable for Reading/Writing an Industry Standard Single Data Rate SDRAM.
  • HUFGEN:Perl based tool for Automatic Generation of Synthesize able VHDL RTL for decoding Huffman code bitstream. The toolintakes Huffman code table/books and generate a ‘state machine’ implementation of a Huffman decoder. It generates a VHDL RTL Core and exhaustive testbench, which can decode a Huffman coded bitstrings. It was used to design the Huffman decoder for ISO 11172-3/ISO 13818 (mp3) audio bit stream. The generated RTL has been proved to work on FPGA.

EXPERIENCE SUMMARY

Organisation: Texas Instruments, Northampton, UK.(1+ Year, Aug 2004-Oct 2005).

PROJECTS:

  • Synthesis,STA and PnR of SERDES CORE I/F Block (90nm).

This project involved RTL-GDS-II flow for small high speed serializer-deserialzer blocks to facilitate high speed chip-to-chip data transmission. RTL pre synthesis was done using Synopsys’ dc_shell, PnR(timing driven) was done using Magma tools, and STA was done using Synopsys’ pt_shell. I was responsible for delivering Layout(DRC/LVS/STA clean) verified to the back end integration team, RTL was given as input. Removing timing errors from the post-layout netlist was the biggest challenge in the project, which was supposed to run at a frequency close to 1GHz.

Organisation : Philips Semiconductors, Southampton, UK(4 Years, Sep 2000-Aug 2004 )

I had worked for Philips Semiconductors with Digital Storage Business line for 3+ years. My Business Unit was responsible for Design/Test of SoCs for CD/DVD storage drives.

PROJECTS:

  • SoC Integration and Full Datapath Verification for the chip called ‘Centaurus’, the main IC on CD/DVD drives(180 nm, 130nm).This task involves integrating various IPs to build a SoC and then verification of the SoC which involved writing test bench, behavioural models to mimic various bus interfaces, bit of embedded C code, editing and tailoring the simulation environment as per needs. The IPs on the SoC were supplied by various other design centres in Europe, and their integration required design of wrappers, both functional and test, and integrating them to form a 400,000 gate SoC. The objective of the task is to integrate the IPs to make the entire system on chip, then run a ‘full chip’ verification of Centaurs IC. ‘Centaurus’ is a SoC which is responsible for reading data from a CD/DVD and delivering the data to the Host Interface’s IDE bus and vice-versa. It involved a DSP processor, a MIPS process, a Buffer Manager, Channel/Encoder Decoder, and various memories. My responsibility was to write all the bus models, update the C-code for MIPS, and then using the full 400,000 gate netlist, run a simulation(with and without SDF), and prove the data integrity. It was considered as a huge daunting task, and it required good communication with teams spread across 3 design centres in Europe, apart from technical knowledge and skills. I was responsible for execution of this task single-handedly. The simulation was done using Cadence’s NC-Sim. Test benches, wrappers and all supporting designs were developed using VHDL.
  • Architecture/Design/Implementation of multi-memory BIST Engine(180nm):The objective of this project was to Design, Implement and Test a generic test shell, which will be able to perform BIST on any memory(s)(and also multiple memories at the same time if required), its integrated to. This design is responsible for performing 11-N/13N algorithm, for the Memory under Test. VHDL was used for RTL. Size of the design was about 30K gates. I was the sole developer/contributor for the project, which started from specs and ended in netlist. Synopsys was used for synthesis. The design was targeted at 250 MHz clock frequency.
  • Design, Synthesis, Verification of DFT logic for(180nm, 130nm) SoC called ‘centarurus’ which is the main IC for CD/DVD drives. The procedure includes design, implementation, integration of various test shells, and Boundary Scan logic on the chip, using various tools, its design and synthesis. I worked very closely with the DFT Architect of the chip on this project and gained a full ‘know-how’ to make a SoC DFTable. Several Perl scripts were also written for Automatic integration of Boundary Scan logic to the SoC, generation and implementation of ‘isolation logic’ to various blocks inside the SoC. The scripts were a great help in cycle time reduction in test logic generation and integration. I filed two patents during the execution of this project as the sole inventor for each of them.
  • RTL Design of Read-Laser Mixed Signal Block.

Organisation: Central Research And Development,ST Microelectronics, Noida, India(2 Years, June 1998-Sep 2000)

Worked as design engineer, withASIC Library Development Group (0.25u).

Here I was responsible for full ASIC library design, development and its validation

SKILL SET

  • Digital Signal Processing Theory and Implementation. Design of Filters, ( FIR, IIR, Adaptive filters) Frequency/Time Transforms, eg MDCT/IMDCT, DCT/IDCT, FFT
  • Detailed Knowledge of ISO/IEC 11172 Part 3 Audio Coding (MPEG-1Audio Layer 3, MP3), some knowledge of AAC(ISO 13818-3) and MPEG-4(ISO11496-10).
  • Specs to RTL coding, proficient in bothVHDL and Verilog. Very efficient in converting specs to RTL, supported by strong background in digital logic design, and extensive experience in producing high quality RTLs, DSP hardware implementation.
  • C,SpecC programming for developing reference Models
  • Embedded Cprogramming, VxWorks.
  • DSP tools System View,Matlab(not very proficient).

Verification: SoC verification, writing testbenches, behavioural models, automation of verification by self-testing test-benches, and using ‘e’ language.

Physical Chip Design including Synthesis, PnR, and STA

  • Design for Test including Boundary Scan, Memory BIST, Scan Based test techniques. Capable of making an SoC DFT-able starting from scratch
  • CMOS circuit design and Simulation. Cell level layout design, DRC LVS using DIVA
  • Knowledge of ARM7 processors from programmer’s point of view.

UNIX shell scripting, Perl scripting: Some of my scripts save considerable manual work, thereby reducing cycle time for development

TOOLS

Experience on most of the leading tools for Simulation(HDL), Synthesis, Timing Analysis, PnR, Simulation(CMOS), including but not limited to Cadence, Mentor Graphics, Synopsys, Magama-da, Symphony-EDA, Verisity.

Strengths

I consider my self to be Confident, Efficient, and Innovative, Self-Motivated,with a drive to make things ‘perfect’.

References

Available on Request