HED: IP Trends

Title: MIPS Tells the EDA World How to Win with IP

By Geoffrey James

Arguably, the most important trend in semiconductor intellectual property (IP) is, well, the lack of a trend. Two years ago, the electronic-design-automation (EDA) vendors jumped onto the IP bandwagon big time. They hoped that IP would provide renewed growth to what was rapidly becoming the most stagnant sector of the software business. Some EDA vendors have been successful in the IP segment. As a percentage of vendor revenue, however, IP has remained basically flat industry-wide—belying the notion that IP was the next big thing for EDA (see the Figure).

To understand where the EDA firms might be encountering limitations, I asked Gideon Intrater, Vice President of Solution Architecture at MIPS, what it takes to build a successful semiconductor-IP business. He identified four key elements:

  1. The IP must really work. This sounds almost ridiculously basic. But there have been plenty of instances in the semiconductor industry where supposedly commercial-grade IP simply wasn’t yet ready for prime time. Intrater specifically cites the example of PCI-controller IP in the late ’90s. “It took over a year for that IP to become stable enough for production use, which translated into expensive delays for products that crutch on the IP,” he explains.
  1. The IP must be efficient. Once again, this sounds pretty basic. But the size and speed of the IP block must be appropriate to the function that it performs. “Designers expect IP to be cheap in terms of manufacturing cost, have low power consumption, and deliver as much performance as possible,” Intrater explains. Yet these desirable requirements are—to a certain extent—mutually exclusive. This aspect forces IP designers to make intelligent tradeoffs. “You have to understand the deeper concerns of the IP customers in order to strike the correct balance,” says Intrater.
  1. The IP must have supporting services. EDA vendors tend to be tool builders, which means that they think of themselves as providing flexible tools that designers use to build their own designs. But an IP block isn’t a tool. It’s a black box that’s supposed to “plug and play” as part of the chip design. Unfortunately, even the best semiconductor IP requires tweaking (and often more than just tweaking) in order to work effectively and efficiently inside a particular chip design. If the designer tries to debug the block (i.e., treat it like a tool), it’s likely to take so long for the designer to get up to speed that it would probably have made more sense for the designer to build the block from scratch. To avoid this, the vendor (who presumably knows the IP block inside and out) must take responsibility for the inevitable tweaking. Some EDA vendors “get” this concept (Synopsys comes to mind). But providing the deepest levels of service support is foreign to the EDA segment as a whole.
  1. The IP must have supporting software. This area is probably where EDA firms face the biggest challenges. In order for IP to be cost effective in a real-world environment, there needs to be a software infrastructure that can utilize the IP in a meaningful way once it’s on the chip. Intrater cites CPU IP as a prime example. “It’s hugely more valuable to a customer if there’s already software that can use the CPU IP in, say, a digital-television or set-top-box environment.” The challenge here is that it can take time to bootstrap a user base that’s willing to create software that utilizes newly forged IP.

In short, IP will continue to play a major role in EDA. But it won’t dominate the EDA industry unless and until the EDA vendors move beyond tool-building to make it the core of their business.

GRAPHIC:

RAW DATA:

2Q05 / 3Q05 / 4Q05 / 1Q06 / 2Q06 / 3Q06
208 / 199 / 209 / 225 / 243 / 246
883 / 923 / 1044 / 990 / 1013 / 1063

Source: EDAC