COLLOQUIUM
Department of Computer Science and Engineering
University of South Carolina
Low Power FPGA Design Techniques for Embedded Systems
Anurag Tiwari
Department of Electrical and Computer Engineering and Computer Science
University of Cincinnati
Date: February 21, 2005
Time: 1:00-2:00PM
Place: Swearingen 1A03 (Faculty Lounge)
Abstract
With the remarkable growth of Field Programmable Gate Array (FPGA) based battery-powered systems, such as personal computing devices, wireless equipment, space-borne systems, and consumer electronics, low power FPGA design is of increased importance. Previous research work shows that dynamic power constitutes a significant portion of total power drawn by an FPGA design. In this presentation, I will show alternate mapping of finite-state machines in contemporary FPGA devices to minimize dynamic power consumption. The objective of this research is to minimize the power drawn by a design without altering its functionality and with minimal or no impact on its timing. The central idea behind the design techniques presented is to reduce the switching activity on the power hungry programmable interconnection network which is used to route a digital signal within an FPGA chip. Power consumed by the clock network which also consumes a considerable amount of power is also reduced by selective clocking of finite state machines. The techniques and algorithms presented can be easily automated and can be incorporated in an existing FPGA design flow.
Anurag Tiwari received the B.Engg degree from National Institute of Technology, Bhopal, MP, India in 1998, and MS and PhD degrees in computer science and engineering from the University of Cincinnati in 2002 and 2005 (completed in January, 2005, and to be conferred in March, 2005), respectively. Since December 2004 he is working as a member of the technical staff in the processor CAD group at Sun Microsystems, Sunnyvale, CA. Previously, he held research engineer position at Center for Development of Telematics, New Delhi, India and research and teaching assistant positions in the department of electrical and computer engineering and computer science at the University of Cincinnati. Anurag Tiwari’s current research and development activities include placement algorithms for microprocessor chips and low power FPGA design techniques for embedded systems.