UNIVERSITY OF CALIFORNIA
College of Engineering
Department of Electrical Engineering and Computer Sciences
Last modified on November 27, 2001 by Hanching Fuh ()
Borivoje Nikolic Homework #9 Solutions EECS 141
Due Thursday December 6, 2001 at 5:00 PM in drop-box outside of 275 Cory
This is your LAST solution set… Hurray!
Problem 1)
a) First, we need to find the skew between the source register clock (f’) and the destination register’s clock (f”). We can do this with a p2 model of the wire and the Elmore delay model.
tf’ = 0.69 (150) (650 f) = 67 ps
tf” = 0.69 [ (150)(650 f) + (150+200)(950) ] = 297 ps
d = tf” - tf’ = 230 ps (eq. 9.1)
Next, we check the race condition to see if the circuit will work properly. Note that the minimum logic delay is a single sum.
d £ tr,min + ti + tl,min (eq. 9.2)
thold + d £ tclk-Q + tsum (modified to include hold time
and to use the given quantities)
100 + 230 £ 300 + 50
330 £ 350 TRUE (barely)... Thus, this circuit has no race problem
Lastly, we find the minimum clock perdiod. Note that the maximum logic delay is a single sum plus the delay of the carry chain.
T ³ tr,max + ti + tl,max - d (eq. 9.3)
T ³ tclk-Q + 31 tcarry + tsum- d + tsetup (modified to include setup time
and to use the given quantities)
T ³ 50 + (31)(250) + 300 – 230 + 150
T ³ 8.02 ns
b) Identical to part a), except the capacitance at f” is much less.
tf’ = 0.69 (150) (650 f) = 67 ps
tf” = 0.69 [ (150)(650 f) + (150+200)(350) ] = 152 ps
d = tf” - tf’ = 85 ps
thold + d £ tclk-Q + tsum
100 + 85 £ 300 + 50
185 £ 350 TRUE ... Thus, no race problem
Note, however, that this circuit has a much better margin of
error than the one from part (a).
T ³ tclk-Q + 31 tcarry + tsum- d + tsetup
T ³ 50 + (31)(250) + 300 – 85 + 150
T ³ 8.17 ns
Note that the minimum cycle time is longer with the smaller skew.
c) Identical to (a), except that the clock in driven in the other direction.
tf” = 0.69 (150) (950 f) = 98 ps
tf’ = 0.69 [ (150)(950 f) + (150+200)(650) ] = 255 ps
d = tf” - tf’ = -157 ps
thold + d £ tclk-Q + tsum
100 - 157 £ 300 + 50
-57 £ 350 TRUE ... Thus, no race problem
Note that this circuit has the best margin of error over all
three cases.
T ³ tclk-Q + 31 tcarry + tsum- d + tsetup
T ³ 50 + (31)(250) + 300 + 157 + 150
T ³ 8.41 ns
Note that the minimum cycle time is the longest over all three cases.
Problem 2)
a) To determine the max. period that we can clock this system, we need to examine every possible path between the synchonous latches and the associated delay.
Min Max
L1àL2 passes through A, B 1ns+1.7ns=2.7ns 2.1ns+2.5ns=4.4ns
L2àL3 passes through C, D .5ns+2.2ns=2.7ns 1.4ns+2.9ns=4.3ns
L2àL4 passes through C, E .5ns+1.5ns=2.0ns 1.4ns+3.1ns=4.5ns
L4àL3 passes through D 2.2ns 2.9ns
L3àL2 passes through B 1.7ns 2.3ns
We want to focus on the minimum delay, because it is this factor which has the potential to through our system into a race condition.
We see that the shortest combinational path is 1.7ns from L3àL2. Since there is also a .3ns tlatch. Thus our Ton must be within 1.7ns+.3ns=2.0ns
b) For the Min. Period that we can clock the system we need to look at the max time:
Tmin=max(comb. Logic) +tlatch=4.5ns+.3ns=4.8ns (note: if there were a setup time specified, we would have to take that into account)
c) Delay = ∑Block Delay + Tlatch
Source Latch / Destination Latch / Min Delay / Max Delay / Skew / Race Constraint / Clock ConstraintMin / Max / d / Min > d + Ton / Max < T + d
L1 / L2 / 3.0 / 4.7 / d / d < 3.0 - Ton / T > 4.7 - d
L2 / L3 / 3.0 / 4.6 / d / d < 3.0 - Ton / T > 4.6 - d
L2 / L4 / 2.3 / 4.8 / 2d / d < (2.3 - Ton)/2 / T > 4.8 - 2d
L4 / L3 / 2.5 / 3.2 / -d / d > -2.5 + Ton / T > 3.2 + d
L3 / L2 / 2.0 / 2.6 / -d / d > -2.0 + Ton / T > 2.6 + d
For min d, use Tmin=4.5ns è consider L1àL2 case: d > 0.2ns
For max d, Consider L4àL3 case: d < 4.5 - 3.2
d < 1.3ns
d) Note that with T = 5.0ns, there is no longer a minimum skew requirement.
From the race constraint column, can see that limiting case is set by L2 -> L4 and L3->L2
Ton < 2.3 - 2d
Ton < d + 2.0
Set 2.3 - 2d = 2.0 + d ==> d= 0.1
Ton < 2.1
Duty Cycle = 2.1/5.0 = 42%
e)
Min / Max / d / Min > d / Max < T + d
L1 / L5 / 1.3 / 2.4 / d / d < 1.3 / T > 2.4 - d
L5 / L2 / 2.0 / 2.6 / d / d < 2.0 / T > 2.6 - d
L2 / L3 / 3.0 / 4.6 / d / d < 3.0 / T > 4.6 - d
L2 / L4 / 2.3 / 4.8 / 2d / d < 2.3/2 / T > 4.8 - 2d
L4 / L3 / 2.5 / 3.2 / -d / d > -2.5 / T > 3.2 + d
L3 / L2 / 2.0 / 2.6 / -d / d > -2.0 / T > 2.6 + d
From L2->L4, d < 1.15;
For Tmax, note that L2->L4 and L4->L3 have opposing behavior.
Set 4.8 - 2d = 3.2 + d
d= 0.53ns
Tmin = 3.73ns
Problem 3)
The 2-T memory cell uses 2 identical transistors with W/L = 0.3/0.2. Separate lines are provided for the read select (RS) and write select (WS), which both switch between 0 and Vdd. The Bit Line is precharged to Vdd/2 prior to a read. A write is done by pulling the Bit Line either to Vdd or to GND. Ignore body effect and channel-length modulation. (g=0; l=0).
a) Explain the operation of the memory. Draw waveforms for BL, WS, and RS and Vx for reads and writes of both ‘1’s and ‘0’s.
To write a ‘1’ to X, set the following:-
BL = Vdd
WS = Vdd
RS’ = Vdd
M1 turns on. Cc is charged to Vdd-Vt. M2 turns on, but has no effect.
To write a ‘0’ to X, set the following:-
BL = 0
WS = Vdd
RS’ = Vdd
M1 turns off. Cc is discharged to gnd. M2 remains off.
To read contents of a cell, set the following:-
BL = Vdd/2
WS = 0
RS’ = 0
If a ‘1’ has been stored in Cc , M2 turns on. The bit line is pulled towards ground. There will be sense amplifiers that signal a dip in voltage along bit line. This dip will be sufficient to register a ‘1’ in the cell.
Conversely, if a ‘0’ has been stored in Cc, M2 remains off. The bit line is unaffected.
b) Determine maximum current through transistors during a read operation.
Consider the following scenario: Vx = Vdd – Vt; VRS’ = 0; VBL = Vdd/2;
Since VRS >VBL, BL is source, and RS’ becomes the drain.
Current thru M2 = kn’ * (W/L)M2 * ((Vdd-Vt)Vdd/2 –Vdd2/4/2)
Substituting kn’ = 110 mA/V2 , Vdd=2.4, Vt = 0.4, Max Current = 280mA
c) The bit line is connected to a single-ended sense amp which has a switching threshold of 200mV in either direction from Vdd/2. Compute the time required to read a data bit. Assume Cc=10fF and Cb=2pF.
Only time the bit line is affected during a read operation is when a ‘1’ has been stored in X.
Current thru M2 (@ VBL = Vdd/2 - 200mV)
= kn’ * (W/L)M2 * ((Vdd-Vt)(Vdd/2-0.2) –(Vdd/2 –0.2)2) = 165mA
Req = 0.5(( Vdd/2 – 0.2) / 165 + (Vdd/2)/280 ) = 5.2kW
t = ReqCb = 10ns
Note: A 200mV movement represents 0.2/1.2 of the total transient
Delay = -ln [1-(0.2/1.2)]t = 0.18t = 1.8ns
Problem 4)
a) When the bitline is driven to Vdd, the transistor operates in saturation region, the maximum voltage is achieved across the storage capacitor when steady state is reached. That is
IS = 0.5 Kn(VG – VS - VT)2 = 0
VS = 4V
b) During READ 1 operation, charge sharing occurs between CS and CBL
CsVS + CBLVBL = (CS + CBL) Vfinal
Vfinal = (50*4 + 450*2.5)/ (50+450) = 2.65 V