CPSC5155 - Introduction to Computer Architecture

CPSC5155 - Introduction to Computer Architecture

Instructor

Dr. Edward L. Bosworth

Center for Commerce and Technology 443

(706) 565-4128

e-mail:
website:

Office Hours – Fall 2006

Monday10:00 AM – 11:00 AM and 2:30 PM – 4:30 PM
Tuesday10:00 AM – 11:00 AM and 2:30 PM – 3:30 PM
Wednesday10:00 AM – 11:00 AM and 2:30 PM – 4:30 PM
Thursday10:00 AM – 11:00 AM

FridayI am not in the office on Friday

I am available to speak with students any time that I am in my office. Please note that faculty meetings are frequently scheduled for 12:30 PM on Wednesdays and Thursdays.

Class Meetings:

Monday and Wednesday4:30 PM – 5:45 PM,
Center for Commerce and Technology, Room 405

Course Prerequisites

CPSC 2105Introduction to Computer Organization

The student is expected to have some familiarity with Boolean algebra; two’s complement arithmetic; basic building blocks such as AND, OR and NOT gates; and MSI components such as encoders, decoders, multiplexers, demultiplexers, and full adders. The course uses assembly language as a functional specification for a computer. The student is expected to be able to understand assembly language statements that will be used to illustrate the design of the computer.

TextbookStructured Computer Organization, Fifth Edition (with CD–ROM)Andrew S. TanenbaumPearson / Prentice–Hall, 2006ISBN 0 – 13 – 148521 – 0

Other Required Materials:None

Page 1 of 7 pagesCPSC5155ULast Revised on November 2, 2018

CPSC 5155Introduction to Computer Architecture
Undergraduate Offering of the Course

Course Description

Review of Boolean algebra and simple combinational and sequential circuits. Study of the design of the major components of a simple computer: memory, central processing unit, and Input/Output systems. Considerable focus on the design of the Control Unit.

Other topics, including examples of real computer architectures, as time allows.

Please see the listing Topics for the Course, attached to this document.

Course Objectives (Learning Outcomes)

At the end of the course the student will be able to describe and explain the following:
1.The top-level architecture of a computer: CPU, Memory, and I/O Component.
2.The basic MSI Circuits (Encoders, Decoders, Multiplexers, Demultiplexers)
and their use in designing combinational circuits.
3.The four basic flip-flop types and their use in design of sequential circuits.
4.The structure of register files as a set of flip-flops.
5.The basic concepts of finite state machines (FSM).
6.The design of modulo-N counters and their use in control units.

7.The basics of the interaction of the CPU and computer memory.
8.Design of computer memory from basic memory chips.
9.The internal structure of the CPU, including the CPU buses, the ALU, the
register file, and the control unit.
10.The construction of the arithmetic-logic Unit (ALU).
11.The control unit as issuing a sequence of control signals; how those control
signals effect the execution of the assembly language statements.
12.Hard-wired and microprogrammed control units.
13.The four basic types of I/O: program-controlled, interrupt-driven, direct memory
access (DMA), and I/O channels.
14.The disadvantages of program-controlled I/O and when it can be used.

15.The basic structure of a vectored-interrupt system.
16.The basic structure of a DMA controller.

Student Responsibilities

1.Attend class regularly.
2.Complete all reading assignments and all homework assignments.
3.Actively participate in all class discussions.
4.Participate in the hands-on laboratory for this course.
The times for these laboratories will be posted.
5.Ask the instructor questions.

Instructor Responsibilities

1.Give lectures on the course material.
2.Assign appropriate homework that illustrates the concepts of the course, and
grade and return the homework in a timely manner with adequate explanation.
3.Give tests over the material, and grade and return the tests in a timely manner.
4.Schedule laboratory sessions at times convenient to the students and provide
for assistance to the students as they complete the lab assignments.
5.Provide a website that supports the course.
6.Provide at least four hours of office time primarily designated for assistance of
students in this class, at times expected to be convenient for the students. It is
expected that the instructor be available to the students during these hours.

Course Methods

This will be an in-class lecture course, taught face-to-face.
There will be a lab component, in which the student will learn by several hands-on
experiences, including:
1)Design and test simple digital circuits, using a commercial circuit simulator.
2)Design and build simple digital circuits using basic digital chips.
3)Write and simulate the execution of a computer program, both at the assembly
language level and the microarchitecture level.

The lab for the course will meet in CCT 450, the same room as used for software labs. The student will be able to complete a lab any time the lab is open and a qualified lab instructor is available. Every attempt will be made to minimize the inconvenience to the student that this extra component of the course will certainly cause.

Mid-Term and Final Exams

All exams for this course will be open-book, open-notes. Students are cautioned not to rely on reading the notes during tests to find the answers, as the questions are only rarely taken directly from previous homework or classroom discussions.

Homework Policy

All homework is due at the beginning of the class on the day assigned. Homework handed in after the start of class will be considered to be late. The penalty for late homework (if assessed) will be 10 points per class period. Homework may not be submitted after the solution has been discussed in class.

Methods for Evaluating Students

The evaluation methods will include homework, a laboratory experience, a mid-term exam, and a final exam, and a simple term project. The relative grading is shown below.

Homework25%
Laboratory Work15%
Mid-Term Exam30%(possibly October 10 or 17)
Final Exam30%(Friday, December 15 at 6:00 – 8:00 PM.)

Assignment of Letter Grades

The method of assigning letter grades based on overall course averages is fairly standard. The basic method for assigning gradesis described as follows:

GRADEPOINTS

A90 – 100D55 - 69
B80 – 89FBelow 55
C70 – 79

Policy on Tests and Final Exams

All in-class quizzes and tests (but not the final exam) will be graded and returned on the following class period. The class meeting immediately preceding the test is devoted to review for the test, and the class period immediately following the test is devoted to return of the test and discussion of all test questions and possible answers.

For all in-class quizzes and tests (but not the final exam), the deadline for requesting a review of the grade is either two weeks after the test is returned or one week before the scheduled date for the final exam, whichever date is earlier.

Please note that a grade review will never lead to reduction of an assigned grade.

Other Course Policies

ADA Accommodation Notice

If you have a documented disability as described by the Rehabilitation Act of 1973
(P.L. 933-112 Section 504) and the Americans with Disability Act (ADA) that may require you to need assistance attaining accessibility to instructional content to meet course requirements, we recommend that you contact the Center for Academic Support in Tucker Hall, room 100 or at (706)568-2330, as soon as possible. It is then your responsibility to contact and meet with the instructor. It is also your responsibility to present the instructor with a letter from the Center for Academic Support. Without this letter detailing the required accommodations, the instructor cannot help you. The Center for Academic Support can assist you and the instructor in formulating a reasonable accommodation plan and provide support in developing appropriate accommodations for your disability. Course requirements will not be waived but accommodations may be made to assist you to meet the requirements. Technical support may also be available to meet your specific need. For more information on services and support available, refer to

Parking

Parking is a problem at CSU; for this we apologize. It is the student’s responsibility to arrive at class on-time and submit any homework before the beginning of class.

Attendance Policy

I do not take roll, but believe that it is important for students to attend class regularly. If you find it necessary to miss one or more classes, you are still responsible for all material covered in the class. You should notify me in advance of expected class absences to avoid late penalties on homework due on the date you miss. For more information on class attendance and withdrawal, refer to

Dropping The Course

We hope that you will complete the course and profit from it. If it is necessary for you to withdraw from the course during the semester, you must follow all official CSU procedures for withdrawing. It is not sufficient to notify the instructor; you must use the ISIS system and withdraw officially. For details on how to withdraw from a course, see the web page

I would appreciate it if you were first to consult with me before starting the procedure for withdrawing from the course. In some cases, we can agree on an arrangement that will allow you to complete the course with minor adjustments.

Academic dishonesty
Academic dishonesty includes, but is not limited to, activities such as cheating and plagiarism. It is a basis for disciplinary action. Collaboration is not permitted on assignments or exams/quizzes in this course. Any work turned in for individual credit must be entirely the work of the student submitting the work. All work must be your own. You may share ideas but submitting identical assignments (for example) will be considered cheating. A simple way to avoid inadvertent plagiarism is to talk about the assignments, but don't read each other's work or write solutions together. Keep scratch paper and old versions of assignments until after the assignment has been graded and returned to you. If you have any questions about this, please see me immediately.

For assignments, access to notes, textbook, books and other publications is allowed. Stealing, giving or receiving any code, diagrams, drawings, text or designs from another person (CSU or non-CSU) is not allowed. Having access to another person’s work on the system or giving access to your work to another person is not allowed. It is your responsibility to keep your work confidential, so that other students do not have access to it without your knowledge. Properly dispose of all your scratch work.

No cheating in any form will be tolerated. The penalty for the first occurrence of academic dishonesty is a zero grade on the assignment or exam/quiz; the penalty for the second occurrence is a failing grade for the course. For exams/quizzes, discussion of any kind (except with me) is not allowed.
( Dishonesty/Academic Misconduct)

CPSC5155: Topics for the Course

1.Brief Overview of the History of Computing
Generations of Computers Based on Technologies
Generations of Computers Based on Usage Patterns
Generations of Computers Based on Economic & Technological Issues
The Idea of Virtual Machines and Its Use in Describing Computer Architecture
Introduction of 3 Sample Computers: Intel Pentium, UltraSPARC III, Intel 8051

2.Overview of Computer Systems Organization
CPU (Central Processing Unit) Organization
The Register Set
The ALU (Arithmetic Logic Unit) and the Three–Bus CPU
The Fetch–Execute Cycle
Instruction Pre–Fetch and Instruction Pipelining
Reduced Instruction Set Computers (RISC) vs. CISC
Organization of Primary Memory
Storing Words in a Byte–Addressable Memory
Big–Endian and Little–Endian Memory Organization
Organization of Secondary Memory
The Input / Output System

3.The Digital Logic Level
Digital Gates and Boolean Algebra
Basic Digital Circuits: Combinational and Arithmetic Circuits
Memory: Latches, Flip–Flops, Registers, and Memory Organization
CPU Chips and Signals
Computer Buses and Signals
Synchronous and Asynchronous Buses: SDRAM and DDR–SDRAM.
Interfacing Devices to Computer Buses
Bus Operations for I/O Devices.

4.The Microarchitecture Level
The Data Path, Microinstructions, and Microinstruction Control
CPU Interface to Primary Memory: Timings and Control Signals
Example Microarchitecture, Including Lab Experiments with a Simulator
Design of the Microprogrammed Control Unit
Design of the Microarchitecture Level
Improving Performance: Improving the ALU Design
Improving Performance: Multi–Level Cache Memory

5.The Instruction Set Architecture Level
Overview of the ISA Level
Numeric and Non–Numeric Data Types
Instruction Formats
Addressing Modes
Instruction Types
Flow of Control
Sample Instruction Sets

6.The Operating System Machine Level
Virtual Memory: Overlays, Paging, and Segmentation
The Working Set Model and the Locality Principle
Interaction of Virtual Memory and Caching
Virtual I/O Instructions
Parallel Processing Issues
Process Synchronization
Example Operating Systems

7.The Assembly Language Level
Introduction to Assembly Language
Lab Experiments in Writing Simple Assembly Language Programs
The Assembly Process
Linking and Loading
Dynamic Relocation and Dynamic Linking
Dynamic Link Libraries (DLL) in MS–Windows
Issues in the Support of Higher–Level Languages

8.Parallel Computing Architectures
On–Chip Parallel Processing and Its Motivation.
Coprocessors
Flynn’s Taxonomy
Shared–Memory Multiprocessors
The Cache Coherence Problem in Multiprocessors
Switching Network Support for Multiprocessors
Message–Passing Multicomputers
Cluster Computing: Google
Grid Computing

Page 1 of 7 pagesCPSC5155ULast Revised on November 2, 2018