Project PlanRev.. 0.9Page 1
Project Golden mantle
University of Portland / School of EngineeringPhone 503 943 73145000 N. Willamette Blvd.Fax 503 943 7316
Portland, OR97203-5798
Project Plan
Project Golden Mantle:
CMOS 8-Bit Analog-to-Digital Converter
Contributors:
Travis Tompkins
Aaron Krizek
Scott Ostrow
Approvals
Name / Date / Name / DateDr. Hoffbeck / Dr. Lillevik
Insert checkmark (√) next to name when approved.
University of PortlandSchool of EngineeringContact: team golden mantle
Project PlanRev. 0.9Page 1
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Revision History
Rev. / Date / Author / Reason for Changes0.9 / 11/04/04 / S. Ostrow, A. Krizek / Initial draft
1.0 / 11/17/04 / A. Krizek / Ind. Rep. Feedback
University of PortlandSchool of EngineeringContact: team golden mantle
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Table of Contents
Summary
Introduction
Product Overview
General Description
Deliverables
Chip Logic Hand Design
*.tpr File
Sample and Hold Prototype
Housing
CPLD Back-up Chip
DAC Component
Pre-Amp Circuitry
Macro Model
CMOS Chip
System Prototype
Development Process
General Approach
Assumptions
Milestones
Risks
CMOS chip fabrication error
Lead times on parts
Clock skew in CMOS chip
Faulty prototype
Use of “off-the-shelf” parts
Schedule
Schedule Overview
Critical Path
Resources
Personnel
Budget
Equipment
Facilities
Contingencies
CMOS chip fabrication error
Lead times on parts
Clock skew in CMOS chip
Faulty prototype
Use of “off-the-shelf” parts
Conclusions
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List of Figures
Figure 1: ADC Design Layout
Figure 2: Golden Mantle schedule
University of PortlandSchool of EngineeringContact: team golden mantle
Project PlanRev. 0.9Page 1
Project golden mantle
List of Tables
Table 1. Project Golden Mantle Deliverables.
Table 2. Project Golden Mantle’s milestones.
Table 3. Project Golden Mantle’s risks.
Table 4. Overall Golden Mantle budget.
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Chapter / Summary1
This document outlines the project plan for Project Golden Mantle. Golden Mantle is a CMOS 8-Bit Analog-to-Digital Converter (ADC) circuit. An ADC converts an analog voltage signal into a series of binary numbers indicating the amplitude of the analog voltage at given points in time. The principal tasks to complete include: B2Logic and BLT design and simulation, VLSI *.tpr file completion, MOSIS chip fabrication, fully functioning prototype without chip, and finally integration of chip in prototype for final working design.
The main section of this document is the chapter: Development Process. Within this segment project assumptions are lined out.It includes the parts that will be purchased or borrowed such as: 8 bit ADC (for prototype), 8-bit DAC (for feedback), comparator, resistors, capacitors, and power supply. These parts will not require any further design besides interfacing them with the rest of the project. Additionally, it is assumed when the VLSI chip arrives it will beintegrated into the prototype with minimal difficulty. Themilestones segment includes the (projected) dates of milestone accomplishment and a brief explanation of each. The milestones discussed begin with our project pre-approval all the way through our final report of the project. The intermediate milestones incorporate the necessary tasks to design and build our project. The last segment of note in the Development Process involves the risks of our design. Each projected risk is explained including the reasoning for the severity assigned and the impact the risk would have if it manifests itself. These risks include faulty designs, late parts arrival, and defective purchased parts. A discussion of risk mitigation is included in the Contingencies section of Chapter 4.
The Schedule section includes an insert of our project timeline produced using MS Project. It outlines required tasks to complete our project through the end of April using As Soon As Possible time constraint. The primary tasks along the critical path during the first semester involve *.tpr file generation to begin the CMOS chip fabrication process, design of the prototype model, and ultimately to the Design Release on December 10, 2004. The critical path during the second semester involves integrating the CMOS chip into the working prototype and ending with the post mortem on April 20, 2005. The next segment describes the resources to be used. This includes people, dollars, and materials. Team members and their respective responsibilities are listed. A table illustrating the budget is provided. We are allotted approximately $200 for the project. The total cost is projected at $1,400. This breaks down into the following: $1200 for the VLSI chip fabrication and $200 for other necessary materials. An NSF Grant covers the cost of the chip fabrication. This section concludes with a listing of equipment and facilities required.
Finally, contingency plans are discussed in the event that any of the previously mentioned risk items prove to be true. For the most part, back-up plans involve falling back on the macro-model and part replacement. Other common options arethe redesign of the specific part of the project that may not work.
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Chapter / Introduction2
The purpose of this document is to outline the intended project plan for The CMOS 8-bit Analog-to-Digital Converter (Project Golden Mantle). This document has been produced for any individual that would like to familiarize him/herself with the step-by-step procedures required to implement Project Golden Mantle.
Readers of this document will benefit by having a thorough understanding of the scheduling involved in Project Golden Mantle. Adequate detail of each task entails duration time, start date, finish date, and any necessary completion of preceding tasks. Additionally, having this project plan drafted will help to ensure successful completion of the project.
This document begins with a product overview to give the reader an understanding of the product and define the deliverables. Next, the development process describes the overall technical and logical sequence that our team will be following. This chapter includes developmental attributes such as assumptions, milestones, risks, schedule, resources, and contingencies that our project depends on in order to be completed. Further detail of each of these sections discusses essential characteristics of Project Golden Mantle.
The main aspect of the plan begins in the fifth chapter, Development Process. Here the reader is provided with the big picture of how the project will be implemented and developmental attributes are defined. The conclusion in chapter six recaps the key points of this document.
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Chapter / Product Overview3
General Description
The circuit will be realized using the tracking ADC architecture. This architecture was chosen due to known high performance in areas of speed and resolution. Also, a primary goal in this project is to integrate the digital components on-chip. The necessary analog components will be implemented off-chip.
Technologies utilized include a MOSIS® Integrated Digital CMOS chip; off-the-shelf fixed function integrated circuits, such as Operational Amplifiers used for comparison and filtering; and discrete electronic components such as resistors, capacitors, LEDs, etc. The most challenging aspect will be successful design of the semi-custom MOSIS® CMOS Integrated Circuit.
Figure 1: ADC Design Layout
Deliverables
Table 1. Project Golden Mantle Deliverables
Date / Deliverable9/08/04 / Pre-Approval Form
9/24/04 / Functional Specification 0.9
9/28/04 / September Program Review
10/08/04 / Functional Specification 1.0 and Approval Meeting
10/18/04 / Initial Chip Discrete Logic Design
10/26/04 / October Program Review
11/05/04 / Project Plan 0.9
11/12/04 / Project Plan 1.0 and Approval Meeting
11/22/04 / Final *.tpr File
11/30/04 / November Program Review
12/10/04 / Design Release and Approval Meeting
1/24/05 / Housing Constructed
1/25/05 / January Program Review
1/31/05 / Complete CPLD Back-up Chip
2/04/05 / Theory of Operations 0.9
2/11/05 / Theory of Operations 1.0 and Approval Meeting
2/16/05 / DAC Component
2/22/05 / February Program Review
2/23/05 / Pre-Amp Circuitry
3/15/05* / CMOS Chip Delivered
3/16/05 / Macro Model Completed
3/25/05 / Final System Assembly and De-bug
3/29/05 / March Program Review
4/08/05 / Prototype Release and Approval Meeting
4/12/05 / Founders Day Presentation
4/15/05 / Final Report 0.9
4/22/05 / Final Report 1.0 and Approval Meeting
*tentative date
Chip Logic Hand Design
The hand design will be implemented, simulated and tested using the B2LogicBLT program.
*.tpr File
The *.tpr file is a netlist of the pin layout and connections for the chip design. It will be created two different ways. First through the BLT program, and then through a hand layout entered in LEDIT.
Sample and Hold Prototype
The sample and hold prototype will consist of actual components (counters, DACs, etc) and will be used to validate the tracking architecture, and determine the sample and hold compensation feature needed for the design.
Housing
The housing is a metal box that conceals all the system components. Material will be metal in order to improve EMI resilience. External ports include an analog signal in port, analog and digital signal out ports, and standard power /ground connections.
CPLD Back-up Chip
A CPLD (Complex Programmable Logic Device) will be programmed to function as a back-up to the MOSIS CMOS chipset in the event of a fabrication or design error. This CPLD will be used in the macro model implementation.
DAC Component
The DAC is an of chip sub-component of the overall system. It is used in the negative feedback loop seen in Figure 1. ADC Design Layout.
Pre-Amp Circuitry
The pre-amp circuitry is not shown in Figure 1, but is used to center an analog input signal around +2.5 volts, and amplify the signal to fill the entire 0-5 volts input range. The pre-amp will include a variable resistance to allow for gain adjustment based on the magnitude of the input signal.
Macro Model
The macro model will consist of discrete components representing the functionality of the CMOS chip. If for some reason the CMOS chip fails to work, the macro model will validate the design.
CMOS Chip
The CMOS chip will be fabricated based on the specifications of the *.tpr file. It will implement two 8-bit counters and a series of 8 digital latches.
System Prototype
The final prototype will be a complete working model of the ADC using the CMOS chip. Data will be taken and compared to the technical specifications to prove the design.
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Chapter / Development Process4
General Approach
Our project involves the design of a CMOS VLSI chip. Because of this, it is imperative that we follow a technical and logical sequence of implementation. It must be logical due to the nature of acquiring the VLSI chip. Initial steps require the chip design and testing using B2Logic software. Once the chip design is set, it is translated into a *.tpr file to be sent to MOSIS for chip manufacturing. Simultaneously, we will begin design of the other off-chip components of the ADC, including off-the-shelf parts simulating the CMOS chip logic. When this working design is tested and de-bugged, the newly arrived CMOS chip will be integrated into the prototype to create the final Prototype Model.
Assumptions
The power supply and simple analog parts will be available from the school.
The VLSI Chip will be delivered on time and in proper working order.
All components of prototype will be available for purchase.
Timing of chip and prototype will meet specs (or be modified) to accurately digitize a 2k analog waveform to within a 5 LSB (least significant bit) accuracy.
Milestones
Table 2. Project Golden Mantle’s Milestones
Number / Description / Original / Previous / Present1 / Product Pre-Approval / 09/08/04 / 09/08/04 / 09/08/04
2 / Functional Spec Approval v1.0
(Approval Meeting) / 10/08/04 / 10/08/04 / 10/11/04
3 / Project Plan Approval v1.0
(Approval Meeting) / 11/05/04 / 11/05/04 / 11/05/04
6 / *.tpr File Completion / 11/24/04 / 11/24/04 / 11/24/04
7 / Off-chip Components Ordered / 12/03/04 / 12/03/04 / 12/03/04
8 / Design Release
(Approval Meeting) / 12/06/04 / 12/06/04 / 12/06/04
9 / TOP’s Approval v1.0
(Approval Meeting) / 02/11/05 / 02/11/05 / 02/11/05
10 / Chip Received From MOSIS / 03/15/05* / 03/15/05* / 03/15/05*
11 / Prototype Release / 04/08/05 / 04/08/05 / 04/08/05
12 / Founder’s Day Presentation / 04/12/05 / 04/12/05 / 04/12/05
13 / Final Report / 04/22/05 / 04/22/05 / 04/22/05
*tentative date of arrival
1. Product Pre-Approval
The initial concept of our project was introduced and approved.
2. Functional Spec Approval
The functional specifications describe the implementation independent details of our project. Approval of this document signifies the product approval.
3. Project Plan Approval
This document explains the schedule we plan to follow to implement our project.
6. *.tpr File Completion
The layout of the VLSI chip is completed by entering the design information into a .tpr file. Once this file is completed and approved, it is sent to MOSIS to fabricate the VLSI chip.
7. Prototype Parts Ordered
We will order parts before the end of this semester so that we can receive them as soon as possible over the Winter Break.
8. Design Release
The design is released at the end of fall semester. Once this happens our design is frozen.
9. Chip Received from MOSIS
This milestone will enable us to test our product and determine if it works.
10. TOP’s Approval
This document is a technical description of our product. It describes the theory of operations of the CMOS 8-bit Analog-to-Digital Converter.
11. Prototype Release
We will have a working demo of our product.
12. Founder’s Day Presentation
The final project presentation.
13. Final Report
This is a report that ties together our accomplishments for the year.
Risks
Table 3. Project Golden Mantle’s risks
Number / Severity / Description1 / High / CMOS chip fabrication error
2 / Medium / Lead times on parts
3 / Medium / Clock skew in CMOS chip
4 / High / Faulty prototype
5 / Low / Use of “off-the-shelf” parts
CMOS chip fabrication error
The MOSIS chip arrives with unsolvable defects. This would result in reliance on a macro model of the digital circuitry integrated onto the faulty chip.
Lead times on parts
The 1 MHz clock frequency at which the design runs is too high for some components. Attempts would be made to find better components or integrate the design circuitry onto a PCB (printed circuit board) to speed function.
Clock skew in CMOS chip
The 1 MHZ clock frequency is too high for the CMOS chip. Attempts would be made to find the highest operating frequency. This new frequency would be the one used in demonstrations as long as it’s high enough to satisfy the design specifications.
Faulty prototype
Nothing seems to work right or there is a bug in the components. Attempts would be made to debug prototype, and would be conducted exhaustively until corrected. If initial prototype cannot be made to work without integration of the CMOS chip, the chips arrival will be for naught. A functional prototype must be developed and working by that time.
Use of “off-the-shelf” parts
Single component pieces of design do not work as expected. New parts will be bought if a solution cannot be found with current part in place.
Schedule
Figure 2: Golden Mantle Project Schedule
Schedule Overview
The above schedule image shows the order and dependencies of required tasks. This schedule can be viewed in more detail in the actual MS Project® file to be made available upon request.
Critical Path
The schedule identifies the critical path to successful project completion. This path outlines the most important tasks to be completed. Items include: accurate hand and simulated logic designs, construction of the *.tpr layout file, ordering off-chip components, construction of the housing, construction of the sub-elements like DAC and pre-amp, and system prototype assembly and debug. The plan illustrates how we will stay on schedule in order to complete the project on time.
Resources
Personnel
Fall Semester
Travis Tompkins: Design and layout VLSI chip, debug *.tpr file.
Aaron Krizek: Research, purchase, and design prototype component layout, debug *.tpr file.
Scott Ostrow: Construct *.tpr file from provided design layout of VLSI chip.
Spring Semester
Travis Tompkins: Build and debug macro-model, Build and debug VLSI chip interface.
Aaron Krizek: Build and debug macro-model, Build and debug VLSI chip interface.
Scott Ostrow: Build and debug macro-model, Build and debug VLSI chip interface.
Budget
Table 4. Overall Golden Mantle budget.
Materials
Prototype Components include parts that will need to be purchased to build the functional prototype to integrate the CMOS chip into.
Services
Fabrication involves our *.tpr file being manufactured into a CMOS chip through MOSIS.
Grants
The cost of both fabrication and prototype will be paid by an NSF Grant and the engineering department of the University of Portland, respectively.
Equipment
Table 5. Equipment
Software / HardwareB2Logic / Lab Equipment Power Supply and DMM
L-Edit / Logic Analyzer
B2Logic – Used for VLSI chip design layout and simulation