Embedded Systems
Mid Semester Exam
February 23, 2012
Maximum Marks: 20
Maximum Time: 1 hour 30 minutes
Question-1: Assume that there are two devices communicating over point to point serial interface. Device 1 wants to transmit a packet of 2 bytes of data to Device 2. Calculate the time required to transmit the packet from Device 1 to Device 2 for each of the following interfaces (Take appropriate care of the necessary overhead in each case):
1. Communication of I2C bus running in standard mode (data rate of 100 KB/s)
2. Communication over SPI bus (also running at 100 KB/s)
3. Communication over SPI bus when Device 1 also wants to read a packet of 2 bytes from Device 2 in addition to the original transmission
Also specify how many microcontroller pins will be required for each of the above three cases [3 marks]
Answer-1:
For I2C, the data format is – 1 start bit, 7 address bits, 1 direction bit, 1 Ack bit, 8x2 data bits, 1x2 ack bits, 1 stop bit
Total bits transmitted = 29 bits
Time required to transmit the data = 29/(100*8*103) = 36.25 μs
Only two pins are required for I2C interface
For SPI, directly data is transmitted over MOSI and MISO. For both half duplex and full duplex communication, number of bits transmitted is 8x2 data bits. Therefore time required = 20 μs.
Four pins are required for SPI interface
Question-2: Answer the following briefly (in 1-3 sentences) [6 marks]
1. What are 4 different types of core microcontroller components, essentially available in every microcontroller unit
2. If a wireless radio is transmitting at 3 dBm, what is the transmit power in mW?
3. If the program memory of a microcontroller is of size 16 kB and memory is organized into 16 bits for each address, what is the minimum size of Program Counter required for such a device?
4. What are three different ways in which a different clock can be provided to a microcontroller component (e.g. a peripheral)
5. Besides the specific sleep modes provided in an Atmel microcontroller, how can one do a finer resolution power management? What precaution should be taken when performing such power management?
6. Why does servicing an interrupt or returning from interrupt incurs a delay?
7. For each of compare and capture mode of Timer/Counter in xMega, specify when does the Buffer Value gets set and reset
8. What are the different reasons for non-determinism in clock synchronization across different nodes in the network?
9. If timer/counter in AVR is working in waveform generation mode and the desired frequency of waveform on WG output is 1/32 of the frequency of timer/counter clock, what is the value you should configure in Compare Channel Register (CCA). Assume prescaler factor for the clock as 1. Specify how you derive your answer
10. For the 16-bit RTC running in xMega, what is the highest resolution you will get if 32.768 KHz clock is selected and what is the maximum timeout period?
11. For the 12-bit ADC in xMega with 3.3V reference voltage, what is the voltage resolution you can get with the ADC?
12. How is error detection implemented within PID field of USB packet? Explain with an example.
Answer-2:
1. CPU, RAM, ROM, Peripherals
2. 2 mW (10 log 2 = 3)
3. 16/2 = 8k addressable locations = 13 bits of addressing
4. Choice of a different clock source, using a different prescaler (clock divide), using a different PLL value (clock multiplier)
5. Use Power Reduction Register to disable the clock to individual peripherals. Resources in use by a peripheral will remain occupied even when the clock to a peripheral is stopped. Therefore, the peripheral should be disabled before stopping the clock to the peripheral.
6. During servicing the interrupt, PC needs to be stored and during returning from the interrupt, PC needs to be restored. Each of these operations require certain delay
7. Compare: BV set on write enable and clear on UPDATE
Capture: BV set on capture signal and cleared subsequently
8. Send time, access time, propagation time (network delay), packet loss, protocol overhead
9. fWG = fCLK/(2N(1+CCA)); therefore configured value of CCA will be 15
10. Highest resolution = 1/32768 seconds; Timeout Period = 216/32768 seconds
11. Voltage resolution = 3.3/212 volts
12. Last 4 bits are reverse of first 4 bits e.g. 01101001 (0x69h)
Question-3: Give full form of the following: [2 marks]
1. UART
2. GPIO
3. ADC
4. I2C
5. SPI
6. USB
Answer-3:
1. Universal Asynchronous Receiver Transmitter
2. General Purpose Input Output
3. Analog to Digital Converter
4. Inter Integrated Circuit
5. Serial Peripheral Interface
6. Universal Serial Bus
Question-4: What is the frequency selection scheme for the Bluetooth communication? Explain your answer with specific details of length of each timeslot, frequency range and number of channels used in the range [1 mark]
Answer-4: Bluetooth uses Frequency Hop Spread Spectrum (FHSS). Each time slot is of width 625 uS. Bluetooth transmitter uses a one of the 71 frequency channels in the range 2.402 – 2.480 GHz in each timeslot as per the specified algorithm while the receiver syncs with the transmitter to get the corresponding data.
Question-5: Assume that we modify the CAN communication to support Wired-OR in place of Wired-AND as is discussed in the class. Assume four bit device ID and for a network where 3 devices, each with id 7, 9 and 10, start transmitting simultaneously, which device will get the bus control after the contention detection phase? Explain how the two loosing device will back off at different stages of bit transmissions. Assume that MSB of id is transmitted first. [1 mark]
Answer-5: In wired-OR logic, dominant bit will be 1
Device-1: 0111
Device-2: 1001
Device-3: 1010
Device-1 will back off after the first bit transmission. Device-2 will back off after the third bit transmission.
Question-6: Are the following task sets schedulable by a static priority based preemptive scheduler? If yes, what priorities would you use? Indicate lowest priority by 1, next higher priority by 2, and so on. Wherever required, show "time lines" at all the relevant critical instants to justify your answers [3 marks]
1. Task T C
A 50 12
B 40 10
C 30 10
2. Task T C
A 80 32
B 40 5
C 16 4
Solution-6:
1. Task set is [(50, 12), (40, 10), (30, 10)].
U = 0.8233 which fails the utilization test for n=3. So we need to do further analysis to decide schedulability. Assign priorities in RM order, so that (30,10) is highest and (50,12) is lowest.
For (30,10), at critical instant R = 10 <= 30. So (30,10) is schedulable.
For (40,10), R = 10 + ceil(R/30)*10 which yields R = 20 <= 40. So (40,10) is schedulable
For (50,12), R = 12 + ceil(R/30)*10 + ceil(R/40)*10 which yields R = 52 > 50. So (50,12) is not schedulable.
So task set is not schedulable.
2. Task set is [(80,32), (40,5), (16,4)]
U = 0.775 which passes the utilization test of Theorem 1. So the task set is schedulable.
Question-7: Assume that you purchased a water level detector system which returns an analog voltage proportional to the level of the water in the tank. You are required to interface your EVK1100 board with this level detector using and sound an alarm when water crosses a height 'h' meters (corresponding to h volts on the sensor output). Assume you need to give high on a GPIO to sound the alarm. Write pseudo code for the level detection application, specifically mentioning the detailed steps required in the following high level steps: [4 marks]
1. Clock selection
2. Initialize GPIO for alarm output
3. Configure ADC
4. Sample ADC periodically and perform the desired action
Solution:
1. Clock Selection:
a. Switching to a specific oscillator
i. Enable the corresponding oscillator
ii. Wait for clock to be ready
iii. Switch to clock from corresponding oscillator
2. Assign and enable pin for GPIO function
a. Enable GPIO control in GPERC
b. Set the pin to output pin
3. Configure ADC:
a. Set pins for ADC function
i. Assign and enable pins for the ADC function
ii. Disable GPIO control in GPERC
iii. Configure pins for the correct function corresponding to ADC
b. Set the mode register to configure the clock for ADC, sample/hold time etc.
c. Enable the ADC channel through cher Register
4. while (1)
Start ADC (by writing into CR register)
val <- ADC_value (After waiting for End of Conversion and then reading the CDR register)
height = val*3.3/212
if (height > h)
Alarm <- 1