Chipset Features Setup Menu
This section allows you to configure the system based on the specific features of the installed chipset. This chipset manages bus speeds and access to system memory resources, such as DRAM and the external cache. It also coordinates communications between the conventional ISA bus and the PCI bus.
DRAM Settings
The first chipset settings deal with CPU access to dynamic random access memory (DRAM).
DRAM Write Page Mode
When enabled, memory access time will be faster than when disabled. Technically, when enabled, RAS (Row Address Strobe) signals will not be generated during page hit; only CAS (Column Address Strobe) signals are generated and DRAM access will be in the page mode during CPU write cycles. Effectively, when enabled, a cycle is eliminated (RAS) and more data is written at once (page mode).
Enabled / Fast memory accessDisabled / Slower memory access
DRAM Code Read Page Mode
This affects CPU DRAM access speeds while program code is being executed. Specifically, if executable code is written in primarily a sequential format, enabling page mode will enable the the CPU to access DRAM more efficiently during read cycles. When disabled, the CPU will not access DRAM in page mode, resulting in slower memory access. On the other hand, if executable code is not mostly sequential (i.e., “jump” and “call” types of instructions are common), disabling this feature would be more beneficial to system performance.
Enabled / DRAM page-mode access enabledDisabled / DRAM page-mode access disabled
DRAM Refresh Mode
The cache DRAM controller offers two refresh modes, Normal and Hidden. In both modes, CAS takes place before RAS but the Normal mode requires a CPU cycle for each. On the other hand, a cycle is eliminated by “hiding” the CAS refresh in Hidden mode. Not only is the Hidden mode faster and more efficient, but it also allows the CPU to maintain the status of the cache even if the system goes into a power management “suspend” mode.
Normal / DRAM refresh using normal CPU cyclesHidden / DRAM refresh without CPU cycle for CAS
Write Buffers
Write buffers are hardware features which improve the overall system performance by allowing the processor (or bus master) to continue its current execution without writing data to its final destination. The data is temporairily stored in fast buffers. The cache-DRAM controller contains three types of write buffers:
1.CPU to DRAM
2.CPU to PCI Bus
3.PCI to DRAM
CPU to DRAM Write Buffer
Enabled / Data will be cached in a fast buffer and CPU will not be interruptedDisabled / Data will be written directly to DRAM and the CPU will be interrupted to control the write operation.
CPU to PCI Write Buffer
When enabled, up to four Dwords of data can be sent to the PCI bus without interrupting the CPU. When disabled, a write buffer is not used and the CPU write cycle will not be completed until the PCI bus signals that it is ready to receive the data.
Enabled / CPU writes are buffered, more data is written and the system operates faster.Disabled / CPU writes are not buffered and the CPU is interrupted.
PCI to DRAM Write Buffer
If enabled, a pair of buffers, with a capacity of four Dwords each, are used to store data written from the PCI bus to memory. When disabled, PCI writes to DRAM are limited to a single transfer.
Enabled / PCI to DRAM writes are bufferedDisabled / PCI to DRAM writes are not buffered
Disabled is the default.
PCI Memory Burst Write
When enabled, the PCI bus will interpret CPU write cycles as the PCI burst protocol. This means that back-to-back sequential CPU memory write cycles addressed to the PCI will be translated into the fast PCI burst memory write cycles. This will directly improve the video performance when consecutive writes are initiated to a linear graphics frame buffer.
Enabled / PCI burst protocol used for successive PCI memory writes.Disabled / Conventional write cycles are used.
Disabled is the default.
Snoop Ahead
This feature is only applicable if the cache is enabled.
When enabled, PCI bus masters can monitor the VGA palette registers for direct writes and translate the writes into the PCI burst protocol for greater speed. This is meant to enhance the performance of multimedia video devices. When disabled, the PCI burst protocol will not be used.
Enabled / PCI burst protocol enabled for VGA writesDisabled / VGA writes not monitored and require standard CPU write cycles.
Disabled is the default.
Cache Features
System BIOS Cache
When enabled, accesses to the system BIOS ROM addressed at F0000H-FFFFFH are cached, provided that the cache controller is enabled.
Enabled / BIOS access cachedDisabled / BIOS access not cached
Video BIOS Cache
As with caching the System BIOS above, enabling the Video BIOS cache will cause access to video BIOS addressed at C0000H to C7FFFH to be cached, if the cache controller is also enabled,
Enabled / Video BIOS access cachedDisabled / Video BIOS access not cached
External Cache Wait State
The wait state is typically a function of the speed of the external cache. For a slower cache, selecting “1WS” will cause the chipset to assert one wait state when accessing the external cache controller. When “0WS” is selected, the chipset will not wait.
0WS / Zero wait state1WS / One wait state
Cache Update Policy
The options for this feature are Write-Back and Write-Through. Write-Through means that memory is updated with data held in the cache whenever the CPU issues a write cycle. On the other hand, Write-Back causes memory to be updated only under certain conditions such as read requests to the memory whose contents are currently in the cache. Write-Back allows the CPU to operate with fewer interruptions, increasing its efficiency.
PCI Posted Write Buffer
When enabled, the system will temporarily write data to a buffer so that the CPU will not be interruped or slowed down. When disabled, the memory write cycle for the PCI bus will be direct to the slower ISA bus.
Enabled / PCI posted writes are bufferedDisabled / PCI posted writes are not buffered
DMA Line Buffer Mode
This feature allows DMA data to be stored in a buffer in order to not interrupt PCI bus operations. When Standard is selected, the line buffer for DMA is in the single transaction mode. Selecting Enhanced allows the line buffer for DMA to operate in an 8-byte transaction mode.
Standard / Single transaction DMA modeEnhanced / 8-byte DMA transaction mode
ISA Master Buffer Mode
ISA master buffers are designed to isolate the slower ISA I/O operations from the PCI bus to enhance the performance of the system. If Standard is selected, the buffer for ISA master transaction is in single mode. If Enhanced is selected, the buffer for ISA master transaction is in 8-byte mode, increasing the ISA master’s performance.
Standard / ISA master in single transaction modeEnhanced / ISA master in 8-byte transaction mode
Memory Hole Start Address
In order to improve performance, certain space in memory is reserved for ISA cards. This memory must be mapped into the memory space below 16 MB. The user defined start address is the beginning address of this space.
The selections are from 1 to 15 with each number in MB. This selection will have no meaning if the memory hole is “disabled” (see below).
Memory Hole Size
This allows the user to define the size of the memory hole reserved for ISA cards. The options are “disabled”, 64KB, 126KB, 256KB, 1MB, 2MB, 4MB, 8MB.
Onboard SCSI Controller
This should be Enabled if a PCI SCSI controller is installed on the motherboard. This allows the PCI controller to scan the SCSI ROM. This should be Disabled if the SCSI controller is absent.
Enabled / PCI SCSI controller installedDisabled / PCI SCSI controller not installed
Delay for SCSI/HDD (Secs)
This is the length of time in seconds the BIOS will wait for the SCSI hard disk to be ready for operation. If the hard drive is not ready, the PCI SCSI BIOS might not detect the hard drive correctly.
The range of selections is from 0-60 seconds.
Power Management Setup
The Power Management Setup allows you to configure you system to most effectively save energy while operating in a manner consistent with your own style of computer use.
Power Management
This category allows you to select the type (or degree) of power saving and is directly related to the following modes:
1.Doze Mode
2.Standby Mode
3.Suspend Mode
4.HDD Power Down
There are four selections for Power Management, three of which have fixed mode settings.
Disable (default) / No power management. Disables all four modesMin. Power Saving / Minimum power management. Doze Mode = 1 hr. Standby Mode = 1 hr., Suspend Mode = 1 hr., and HDD Power Down = 15 min.
Max. Power Saving / Maximum power management -- ONLY AVAILABLE FOR SL CPU’S. Doze Mode = 1 min., Standby Mode = 1 min., Suspend Mode = 1 min., and HDD Power Down = 1 min.
User Defined / Allows you to set each mode individually. When not disabled, each of the ranges are from 1 min. to 1 hr. except for HDD Power Down which ranges from 1 min. to 15 min. and disable.
PM Control APM
When enabled, an Advanced Power Management device will be activated to enhance the Max. Power Saving mode and stop the CPU internal clock.
If the Max. Power Saving is not enabled, this will be preset to No.
VGA Adapter Type
When enabled, this feature allows the VGA adapter to operate in a power saving mode. The options are Green and Non-green.
The following four modes are Green PC power saving functions which are only user configurable when User Defined Power Management has been selected. See above for available selections.
Doze Mode
When enabled and after the set time of system inactivity, the CPU clock will run at at slower speed while all other devices still operate at full speed.
Standby Mode
When enabled and after the set time of system inactivity, the fixed disk drive and the video would be shut off while all other devices still operate at full speed.
Suspend Mode
When enabled and after the set time of system inactivity, all devices except the CPU will be shut off.
HDD Power Down
When enabled and after the set time of system inactivity, the hard disk drive will be powered down while all other devices remain active.
Wake-Up Events
When one of the following four Wake Up Events is enabled, any event from an input device connected to the associated IRQ will cause the system to “wake up” from any of the above modes.
IRQ 3 (Wake-Up Event)
IRQ 3 is commonly associated with COM 2.
IRQ 4 (Wake-Up Event)
IRQ 4 is commonly associated with COM 1.
IRQ 8 (Wake-Up Event)
IRQ 8 is associated with the Real Time Clock Alarm.
IRQ 12 (Wake-Up Event)
IRQ 12 is often associated with a PS/2-style mouse.
Power Down Activities
Even though the system may be in a power saving mode, some devices can be used (accessed) without waking up the system. An example would be to receive a fax through a serial port and print it through the LPT printer port while the system is in a “sleep” mode. Similiarly, device activity will not prevent the system from going into a power saving (sleep) mode.
The following entries allow the user to determine which devices are to be available. Settings are either On or Off. Off is the default.
COM Ports Accessed
Selecting On allows you to use the serial ports, COM 1, COM 2, COM 3 and COM 4, without causing the system to enter or leave a “sleep” mode.
LPT Ports Accessed
Selecting On means that it is possible to print while the system is in “sleep” mode.
Drive Ports Accessed
Selecting On means that disk drive activity will not prevent the system from going into “sleep” mode or “awaken” it.
The following is a list of IRQ’s, Interrupt ReQuests, which can be exempted much as the COM ports and LPT ports above can. When an I/O device wants to gain the attention of the operating system, it signals this by causing an IRQ to occur. When the operating system is ready to respond to the request, it interrupts itself and performs the service.
As above, the choices are On and Off. Off is the default.
When set On, activity will neither prevent the system from going into a power management mode nor awaken it.
IRQ1 (Keyboard)
IRQ3 (COM 2 )
IRQ4 (COM 1)
IRQ5 (LPT 2)
IRQ6 (Floppy Disk)
IRQ7 (LPT 1)
IRQ8 (RTC Alarm)
IRQ9 (IRQ2 Redir)
IRQ10 (Reserved)
IRQ11 (Reserved)
IRQ12 (Reserved)
IRQ13 (Coprocessor)
IRQ14 (Hard Disk)
IRQ15 (Reserved)
PCI Configuration Setup
This section describes configuring the PCI bus system. PCI, or Personal Computer Interconnect, is a system which allows I/O devices to operate at speeds nearing the speed the CPU itself uses when communicating with its own special components. This section covers some very technical items and it is strongly recommended that only experienced users should make any changes to the default settings.
PCI Slot Configuration
Latency Timer
Since the PCI bus is operating at a speed very much higher than a standard ISA bus, the PCI bus must be slowed down when interacing with the standard bus. This feature allows the you to define how long the PCI bus will delay. This number is dependent on the PCI master device in use and varies from 0 to 255.
Slot PIRQ#
A PIRQ is an interrupt request which is signaled to and handled by the PCI bus. The current PCI standard allows for four PIRQs; in this case, they are called PIRQ0#- PIRQ3#.
However, since the operating system usually has the final responsibility for handling I/O, PIRQs can be mapped to an IRQ if the device occupying a given slot requires an IRQ service.
In sum, you can select which PIRQ is associated with each PCI slot (“Slot x Using PIRQ#”) and which conventional IRQ is associated with eachPIRQ (“PIRQx# assigned IRQ”). Some motherboards use jumpers to associate IRQs with PCI slots. In such a case, the IRQ settings must be the same as the jumper settings on the motherboard.
A setting of NA means the IRQ has been assigned to the ISA bus and is not available to any PCI slot.
NCR Latency Timer
This feature allows you to define the time delay for data movements between the PCI SCSI controller and the slower standard bus. The units are clock ticks of the PCI clock which operates at 33mhz.
NCR/810 Using PIRQ#
This allows you to select a PIRQ for the NCR PCI 53C810 controller.