Homework #3 – Transmitter Multiplexing
DUE DATE: May 3rd, 2007
Plot all transmitter outputs: the pre-amp outputs, the transmitter output, and receiver input.
1. Transmitter Pre-Amp / Multiplexing
a) 2:1 Multiplexing with 5GHz Square Waves
From problem #2, you have built a 10Gb/s, 400mV output driver:
You can ignore the transmitter pre-emphasis for this particular homework. (There is an obvious extension of how this would extend to other pre- and post- tap equalization.)
Create the data multiplexing for nodes ‘Din’ and ‘Dinb’. Since nodes Din and Dinb are large capacitances, you will need a low swing, high bandwidth pre-amp.
The values Data0 and Data0b are digital values which are obviously complementary. Create the value Data0 and Data0b by the same random digital data symbol (but obviously opposite polarities), with 50ps rise time and 150ps hold time (PWL), using the script “prbs.pl”.
Use a complementary square wave clock “CLK” and “CLKb”, which are 50ps rise time, 50ps hold time square waves, which are out of phase by 180 degrees.
You will need to offset the Data0 and Data1 voltages by 100ps offset from each other, so that there is enough set-up, hold time for the clock phases.
You have several choices of multiplexers at your disposal:
A Resistive Bandwidth Extension
Here obviously the clock edges CLK and CLKb are coming directly from the on-die 5GHz Phase Locked Loop.
B. Digital Multiplexing with Large Bandwidth Pre-Amp
Another type of output driver is above, where the 5Gb/s input data is first digitally multiplexed to 10Gb/s at Ain0_10G and Ain0b_10G, which then drive the Pre-Amp. This type of pre-amp limits the output swing of DIN and DINB. When DIN or DINB start going to low, they turn on the PMOS and the resistor begins pulling the drain node higher.
You can also explore using the digital multiplexer to give you 10Gb/s data values ‘Ain0_10G’ and ‘Ain0b_10G” which would drive the Resistive Bandwidth Extension circuit with only 1 NMOS pulldown as opposed to the 2 NMOS series.
2.
Do one of the following:
a) 2:1 Multiplexing with 5GHz Sine Waves
Replace the 5GHz square wave clocks with 5GHz sine waves – of amplitude 700mV. (with Vdd=1.0V in 90nm) (DC value can be adjusted through AC coupling, so you can change the DC bias of the sine clocks). The reason this waveforms are sinusoidal is that the clocks are coming from an 5GHz on-die LC oscillator (for low jitter generation).
b) 4:1 Multiplexing with 4 phase, 2.5GHz Square Waves
Assume the 4 phases, 2.5Ghz clocks come from an on-die ring oscillator. Create 4 digital data streams @ 2.5Gb/s (50ps rise time, 350ps hold time). Also create 4 clock phases (50ps rise time, 200ps hold time), with each phase offset from each other by 100ps.
There are two possible architectures for the multiplexer, among possibly others:
The problem with the above is low speed of the pulldown 3 stack NMOS. An alternative structure you may try is combining the 3 stack NMOS into 2 stack NMOS using dynamic NAND gates in combination with the clock.
See the paper at: http://mos.stanford.edu/papers/cky_jssc_12_96.pdf. Page 2021, for doing the combination of clock with data using a dynamic gate.
3. 2:1 Multiplexer with 5GHz Square Waves, but with Clock Asymmetry
Resimulate problem 1, but now recognize that it is impossible to obtain equal rise/fall 5Ghz clock waveforms.
Instead, notice that a PLL needs to go through several stages of buffering before it is used at the 2:1 multiplexer. Such buffer stages will cause phase and rise/fall time mismatches.
Use 5GHz clock waveforms, but make them asymmetric by making one phase offset by the other by 10ps, and also make the rise time of the “slower” clock phase by 70ps instead of 50ps.
Notice how the eyes coming out of the transmitter output are asymmetric from each other.