Project Plan Rev. 0.1 Page ii
Project Bluebird
University of Portland / School of Engineering Phone 503 943 73145000 N. Willamette Blvd. Fax 503 943 7316
Portland, OR 97203-5798
Final Report
Project Pitroach: BLT
(B2Logic to L-Edit Translator)
Contributors:
John Chezem
Zachary Heath
Daman Oberoi
Approvals
Name / Date / Name / DateDr. Osterberg / Dr. Lillevik
Insert checkmark (√) next to name when approved.
University of Portland School of Engineering Contact: Zachary Heath
Final Report Rev. 0.9 Page ii
Project Pitroach up-EE-tr-04-07
Revision History
Rev. / Date / Author / Reason for Changes0.9 / 04/15/04 / Team Pitroach / Initial draft
University of Portland School of Engineering Contact: Zachary Heath
Final Report Rev. 0.9 Page ii
Project Pitroach up-EE-tr-04-07
Acknowledgements
We would like to begin by thanking our faculty advisor, Dr. Peter Osterberg. Without his motivating presence, we would never have been able to complete the project in a timely manner. We would also like to thank our industry representative, Mr. Dave Dunning. His feedback on our formal documents and ideas for our project inspired what is now BLT. Finally, we would like to say thanks to Dr. Sigurd Lillevik, Dr. Mary Jane Willshire, and Dr. Wayne Lu for their guidance and support. Without the help of these people, BLT would not have such a high level of success.
Table of Contents
Summary 1
Introduction 3
Background 4
Methodology 7
General Approach 7
Assumptions 7
Milestones 7
Risks 9
Insufficient Testing 9
Faulty Chip 9
Resources 9
Personnel 9
Budget 10
Software 10
Contingencies 10
Insufficient Testing 10
Faulty Chip 11
Results 12
General Description 12
Technologies 12
B2Logic v.3.0.15 (Windows only) 12
Tanner's L-Edit (UNIX and Windows) 13
Practical Extraction and Report Language (PERL) 13
Software Design 13
Hardware Design 15
12 Mini Circuits 15
24 Hour Clock 16
Process Evaluations 17
Assumptions 17
Milestones 18
Risks 18
Resources 19
Contingencies 19
Conclusions 20
Appendix A 22
Appendix B 24
University of Portland School of Engineering Contact: Zachary Heath
Final Report Rev. 0.9 Page ii
Project Pitroach up-EE-tr-04-07
List of Figures
Figure 1. B2Logic Sample Circuit…………………………………………………………………………….4
Figure 2. IC Development Process without BLT……………………………………………………………5
Figure 3. IC Development Process with BLT……………………………………………………………….5
Figure 4. Software Architecture of BLT System……………………………………………………………12
Figure 5. 24 Hour Clock Layout in B2Logic…………………………………………………………………16
Figure 6. 24 Hour Clock MOSIS IC………………………………………………………………………….17
University of Portland School of Engineering Contact: Zachary Heath
Final Report Rev. 0.9 Page ii
Project Pitroach up-EE-tr-04-07
List of Tables
Table 1. Key Pit Roach Milestones. 8
Table 2. Pit Roach Project Risks. 9
Table 3. Overall Pit Roach Budget. 10
University of Portland School of Engineering Contact: Zachary Heath
Final Report Rev. 0.9 Page ii
Project Pitroach up-EE-tr-04-07
Chapter / Summary1
Our product, B2Logic to L-Edit Translator (BLT), will fill a current void at the University of Portland by significantly increasing the speed and ease of the integrated circuit (IC) layout process. The program takes the name of the B2Logic netlist and the number of pins on the IC package as inputs. BLT will parse the B2Logic netlist and format the output file accordingly. This newly created .tpr file can then be used as input to the L-Edit Auto Place and Route function to automatically create the IC layout. BLT will eliminate the need for hand writing .tpr files, which is an error-prone and tedious process.
Our Microsoft Project schedule lists the tasks we needed to accomplish, along with deadlines for completion. The deliverables in this project included milestone documents, presentations, and design schematics. The milestone documents were the Pre-Approval Form, Functional Specifications, Project Plan, Design Checklist, and Theory of Operations. Other design deliverables included the schematic for the 24-Hour Clock, test chips, monthly review presentations, and test .tpr files. Our original assumptions and potential risks are clearly stated along with the contingency plans for addressing the risks. The major risks included insufficient testing and faulty CMOS chips. The predicted project resources are described, including people, fabrication costs, and software. Since the major costs were accounted for by a National Science Foundation grant, the critical resource was personnel and time.
This document also describes details about the architecture and implementation of project Pit Roach. The document starts by giving a broad introduction and background into the Pit Roach project. Then, BLT's architecture will be thoroughly analyzed and explained using a top-down approach. Finally, we delve into the intricacies of BLT's operation and implementation.
The motivation for BLT was to save a tremendous amount of time for University of Portland students implementing circuits in silicon. Currently, students must hand write .tpr files and check them multiple times for accuracy. With BLT, students will not only have their .tpr file in a matter of seconds, but they can be confident that the information is free of errors. The success and demand of BLT at the University of Portland will determine whether or not the software will be shared outside of this university.
The process by which BLT performs its function is straightforward and specific. Since both the B2Logic netlist and .tpr file formats are standard, logical, and predictable, a formula was developed to translate the netlist into the properly formatted .tpr file. This recipe is detailed in the Results section.
This document outlines the entire life of Project Pit Roach, which culminated in successfully creating BLT. We will discuss what could be done to improve BLT’s design and functionality, and what we would do to improve our process. This is to allow anyone working on a similar project to easily incorporate what we have learned for the betterment of their work.
University of Portland School of Engineering Contact: Zachary Heath
Final Report Rev. 0.9 Page ii
Project Pitroach up-EE-tr-04-07
Chapter / Introduction2
The purpose of this document is to inform the University of Portland (UP) faculty, staff, and students about Project BLT’s conclusion. This document includes a functional project overview, the methodology behind the development and testing of BLT, a detailed description of the uses and effects that BLT will have on future generations of UP students, and a list of resources for further study and use of BLT. The methodology is composed of the assumptions, milestones, and risks associated with Project Pit Roach. A Microsoft Project schedule, which initially forecasted the completion dates for all tasks, is also included. The predicted required resources to accomplish the milestones are presented. These resources include personnel, time, and computer software needed for coding and testing. The results section will include screen shots of BLT in action, as well as a complete discussion of how BLT works and can now be used.
After reviewing this document, the reader should have a sound understanding of how BLT became what it is today, as well as the fundamental knowledge needed to utilize the power that is BLT. This document provides an explanation of the project development methodology, the results of completing BLT, and a list of other resources that may be utilized for the further study and use of the BLT translation tool.
University of Portland School of Engineering Contact: Zachary Heath
Final Report Rev. 0.9 Page ii
Project Pitroach up-EE-tr-04-07
Chapter / Background3
Project BLT is a translation program that will take the netlist (a .edf file) from B2Logic and convert it to a Tanner .tpr file. This will enable students creating a VLSI chip to go directly from a high-level circuit schematic to the VLSI chip design layout with little manual work in between.
Currently, University of Portland students designing VLSI chips have to hand write the Tanner .tpr file after extensively testing their circuits in B2Logic. It is extremely easy to make a simple mistake during this process due to the length, complexity, and accuracy required in the .tpr file for Tanner’s Auto Place and Route function. Although Tanner’s full suite includes its own “Digital Simulator Program” to L-EDIT translator, the University of Portland has elected to postpone purchase of this program due to its expense and the fact that if we used this program, we would have to abandon the use of B2Logic.
B2Logic is a high-level digital circuit schematic simulator that allows the user to ‘drag and drop’ logic gates to form complex digital circuits. The figure below shows a screenshot of a sample circuit in B2Logic.
Figure 1. B2Logic Sample Circuit.
This circuit must then be saved as a EDIF netlist that identifies the unique layout of each circuit design. This will allow easy identification and parsing of the specific parts and connections used in each design. The netlist will then be run through BLT, and a Tanner .tpr file will be produced. This .tpr file is the text equivalent of a complete VLSI Layout, and can be used by L-Edit’s Auto Place and Route function to layout a complete VLSI chip.
There is currently a software gap between the B2Logic and L-Edit CAD tools that will be filled by the completion of BLT. This process is shown in Figure 2.
Figure 2. IC Development Process without BLT.
With the addition of BLT, students will be able to automate the .tpr creation process as seen in Figure 3. This will allow students to spend more time designing more complicated circuits, testing and debugging their circuits, and will provide a means by which they can create a .tpr file in a way that is both fast and error proof.
Figure 3. IC Development Process with BLT.
Therefore, the completion of BLT will have two primary benefits:
1) It will fill the current void between B2Logic and L-Edit for students at the University of Portland and make chip design a much simpler process.
2) It will give the University of Portland an important piece of software for very little or no cost.
University of Portland School of Engineering Contact: Zachary Heath
Final Report Rev. 0.9 Page ii
Project Pitroach up-EE-tr-04-07
Chapter / Methodology4
General Approach
The general approach of the schedule was to complete the design, coding, and testing of the BLT software during the first semester. In the second semester we expected to receive the test chips from MOSIS, modify the current test bed, and complete BLT bonus features, such as a graphical user interface and/or a UNIX command-line executable.
Assumptions
Listed below are the original assumptions made in the design and implementation plan:
n Digital circuit designed in B2Logic version 3.0.15a
n Logic gates used in digital circuit design are selected from the BLT library
n Logic gates used in digital circuit design comply with BLT design rules
n Exported .tpr file is in the same directory as BLT
Milestones
Below is the original table of the primary project milestones. Each item is also briefly discussed.
Number / Description / Original09/26/03 / Previous
09/26/03 / Present
09/26/03
1 / Product Approval / 10/09/03 / 10/09/03 / 10/09/03
2 / Project Plan Approval / 11/03/03 / 11/03/03 / 11/03/03
3 / Chip Send-Off / 11/26/03 / 11/26/03 / 11/26/03
4 / Design Release / 12/05/03 / 12/05/03 / 12/05/02
5 / Theory of Operations Approval / 02/11/04 / 02/11/04 / 02/11/04
6 / Macro Model Operational / 02/16/04 / 02/16/04 / 02/16/04
7 / UNIX-Compatible Version / 03/01/04 / 03/01/04 / 03/01/04
8 / Graphical User Interface / 03/15/04 / 03/15/04 / 03/15/04
9 / Prototype Release / 04/08/04 / 04/08/04 / 04/08/04
10 / Founder’s Day Presentation / 04/13/04 / 04/13/04 / 04/13/04
11 / Instruction Manual / 04/18/04 / 04/18/04 / 04/18/04
12 / Final Report / 04/20/04 / 04/20/04 / 04/20/04
13 / Post Mortem Presentation / 04/26/04 / 04/26/04 / 04/26/04
Table 1. Key Pit Roach Milestones.
- Product Approval is achieved after the requirements for the project have been fully defined.
- Project plan approval is accomplished upon the completion and approval of the Functional Specifications 1.0 document.
- Chip send-off will occur upon the completion of the BLT design, programming, and .tpr file accuracy testing.
- Design release is achieved upon completion of the design checklist.
- Following completion of the design checklist, the theory of operations document can be submitted for approval.
- An operational macro model mean the 24 hour clock is operating correctly with the microchip.
- A UNIX version of BLT is a bonus feature that would be ideal to implement.
- A graphical user interface would give BLT an interface beyond an executable icon or a command prompt.
- Prototype release is achieved after receiving the CMOS chip from MOSIS, completing the test bed, and adjusting any identified errors.
- The Founder’s Day presentation is the final presentation regarding the process involved in creating BLT.
- The final report is the culmination of the senior design project and will be turned in after all prior steps of the project, including the Founder’s Day presentation, have been completed.
- The post mortem presentation is the final assignment for the senior design class and will be presented after all other work for the project has been completed.
Risks
Table 3 below lists risks that we originally thought might be problems for Project Pit Roach. Each risk is further discussed following the table.
Number / Severity / Description1 / High / Insufficient Testing
2 / Low / Faulty Chip
Table 2. Pit Roach Project Risks.
Insufficient Testing
It is critical that we extensively test BLT within our given time constraints. This is a high risk, because, without sufficient testing, we cannot be confident that BLT will successfully perform translation for any digital circuit.
Faulty Chip
Although there is a relatively small chance, hence the low severity rating, it is possible that MOSIS develops a faulty chip, even if it was correctly designed.
Resources
This section outlines the resources we initially expected to use. This includes people, capital, and software.
Personnel
n Zach Heath: Student designer and first semester project manager.