INFN-FE, Angelo Cotta Ramusino 2013-10-30
na62_trig_rqst_buffer module description
last modified 2013-10-30
module na62_trig_rqst_buffer (
// inputs:
clk_40MHz,
reset_n,
dram_init_done,
BCntRes_fromTTCrq,
EvCntRes_fromTTCrq,
L1Accept_fromTTCrq,
BCntStrb_fromTTCrq,
EvCntHStrb_fromTTCrq,
EvCntLStrb_fromTTCrq,
BCntEvCntData_fromTTCrq,
read_req_trigproc_phyclk,
dbg_trig_gen_enable_in, // acr 2012-08-10
pause, // don't generated triggers until the hit generators, the receivers the latency buffers and so on have been initialized
// outputs:
read_trig_req_ack, // acr 2010-06-13 the acknowledge/trigger data valid flag is needed to synchronize the module's 40MHz operation to the faster clock domains of the calling modules
empty_trig_fifo,
full_trig_fifo,
trig_tstamp_out, // acr 2010-06-12 sending out the trigger time stamp to use it in the event header
L1Accept_data_out, // acr 2012-11-26 sending out the L1Accept data to use it in the event header
pointer_to_dram_bank, // acr 2010-06-10 using the 8 banks one can extend the latency to 838,8608 ms
pointer_to_dram_row, // acr 2010-05-28 a row holds one frame which is 6.4us wide -> 2^14 rows correspond to 104,8576 ms
pointer_to_dram_col, // acr 2010-05-28 a row is divided into 16 "windows" ( a "window" holds hits collected in a 400ns period )
number_windows_to_read,
trig_fifo_usedw, // acr 2010-05-28 a 16 location trigger FIFO should be enough
end_of_frame_pulse_40MHz,
frame_ID_40MHz,
Event_counter_local, // acr 2012-11-26
Bunch_counter_local, // acr 2012-11-26
L1Accept_dummy_out, // acr 2012-11-26
BCntStrb_dummy_out, // acr 2012-11-26
EvCntHStrb_dummy_out, // acr 2012-11-26
EvCntLStrb_dummy_out, // acr 2012-11-26
BCntEvCntData_dummy_out // acr 2012-11-26
);
// NOTE: THE VALUES LISTED FOR THE PARAMETERS ARE DEFAULT VALUES WHICH ARE GENERALLY REDEFINED BY MODULES HIGHER UP IN THE DESIGN HIERARCHY
parameter NUMBER_OF_TRIGGERS_IN_A_FRAME = 1;
parameter TRIGGER_LATENCY_IN_CLK_CYCLES = 128;
parameter seed = 129;
parameter FIFO_NUMWORDS = 64;
parameter FIFO_WIDTHU = 6;
parameter DRAM_BANK_PTR_WIDTH = 2;
parameter DRAM_ROW_PTR_WIDTH = 14;
parameter DRAM_COL_PTR_WIDTH = 10;
parameter IN_WINDOW_ADR_WIDTH = 6; // acr 2010-06-10 2^6 = 64 locations to store all hits in a "time window"
parameter COUNTER_16_WIDTH = 4; // acr 2010-06-10 2^4 = 16 clock cycles which are equivalent to the "time window" span of 400ns
parameter TRIG_T_STAMP_WIDTH=DRAM_BANK_PTR_WIDTH + DRAM_ROW_PTR_WIDTH + (DRAM_COL_PTR_WIDTH - IN_WINDOW_ADR_WIDTH) + COUNTER_16_WIDTH; (=24)
parameter frame_ID_WIDTH = 16; //acr 2010-09-02
· Clock domain(s):
o “clk_40MHz” : in; it is the basic TTC clock (40.08MHz) to which all the real or simulated TTC signals are synchronous
· Overview:
The “na62_trig_rqst_buffer” module’s main function is to buffer all the information connected to the TTC L1Accepts into a “trigger request FIFO” from which the trigger data is extracted when the “latency buffer” realized in the external DDR2 SDRAM memory is available for read access. The “na62_trig_rqst_buffer” module’s analyzes the L1Accept data to determine the address and the number of data windows to be fetched from the DDR2 memory and send to the “na62_trig_match_packet_builder” module for trigger matching and output packet building. In order to determine the address of the portions of DDR2 memory to be read, the “na62_trig_rqst_buffer” records the value of a local “bunch crossing” counter at the time of arrival of the L1Accept pulse and subtracts from it the value defined by the macro TRIGGER_LATENCY_IN_CLK_CYCLES. da verificare!!
· Detailed informations:
The “trigger_fifo_vhd” trigger request FIFO is 60 bit wide and 64 positions deep. The “trigger_fifo_data” input data is defined as follows:
· trigger_fifo_data = { L1Accept_data (36 bit wide), trigger_timestamp (24 bit wide) };
where:
o L1Accept_data is a 36 bit wide word built with the trigger information delivered by the TTC assuming it is operating in the “11” mode summarized by the diagram to the right:
L1Accept_data = { TTC_EvCnt(24 bits) , TTC_BCnt(12 bits) }; (event count and bunch count)
o trigger_timestamp is a 24 bit register which is loaded with the contents of the “latency_corrected_clk_counter” when the signal “L1Accept_fromTTCrq” is active. The “latency_corrected_clk_counter” is loaded with the value:
24’d0 -TRIGGER_LATENCY_IN_CLK_CYCLES when either input is active among:
§ the general module’s reset_n
§ BCntRes_fromTTCrq
§ pause ( a signal to the simulated trigger generator section of this module to stop until all parts of the design hierarchy, such as the DDR2 SDRAM buffer for instance, are initialized)
The “trigger_fifo_data” is written into the trigger request FIFO one “clk_40MHz” cycle after the arrival of the “EvCntHStrb_fromTTCrq” signal (real or simulated).
The “trigger_fifo_data_out” is read from the FIFO upon activation of the “read_req_trigproc_phyclk_pulse”; this signal is derived by the “read_req_trigproc_phyclk” input, which is a level set by a module in the “phy_clk” domain and cleared by the driving module upon receiving the “read_trig_req_ack” signal from this module; the “read_trig_req_ack” is simply the “read_req_trigproc_phyclk_pulse” delayed one clock cycle.
The “trigger_fifo_data_out” is used to set the value at two output ports of this module:
· the “L1Accept_data_out” port = “trigger_fifo_data_out”[59:24]. “L1Accept_data_out” = { TTC_EvCnt(24 bits) , TTC_BCnt(12 bits) }
· the “trig_tstamp_out” port = “trigger_fifo_data_out”[23:0]. “trig_tstamp_out” = contents of the “latency_corrected_clk_counter” which was sampled upon the arrival of the signal “L1Accept_fromTTCrq”
These ports provide the information about the L1Accept that needs to be included in the trigger-matched data packet sent to the DAQ’s subdetector PC.
The “trigger_fifo_data_out” is also used to set the value at the following output ports of this module:
· pointer_to_dram_bank = { 1’b0, trig_tstamp_fifo_out[ 23: 22]}. NOTE THAT bank[2] is set to 1’b0.
· pointer_to_dram_row = trig_tstamp_fifo_out[ 21 : 8]; NOTE THAT a row holds one frame which is 6.4us wide -> the 2^14 rows of one SDRAM bank correspond to 104,8576 ms
· pointer_to_dram_col broke down as shown below:
o pointer_to_dram_col[9:6] = trig_tstamp_fifo_out[ 7 : 4]; NOTE THAT a row is divided into 16 "windows" ( a "window" holds hits collected in a 400ns period )
· pointer_to_dram_col[5:0] = 6'd0; this is simply the pointer to the base of the memory page containing one “timing bucket”
· number_windows_to_read = 2’d1; temporarily set to a constant value; actually if a trigger time stamp is close to one edge of the “bucket window” then the number of windows to read should be set to 2. If a trigger time stamp is close to the lower edge of a bucket then the base pointer should be set to the base pointer of the preceding bucket, unless this means to point to the preceding DDR2 SDRAM row (TODO: check whether this processing is carried out in another module)
The “na62_trig_rqst_buffer” module has an additional set of outputs used to simulate the L1Accept while debugging the design suite:
· end_of_frame_pulse_40MHz, frame_ID_40MHz: the “na62_trig_rqst_buffer” module contains a counter which is kept reset until the DDR2 SDRAM buffer is initialized and it is reset also in response to the BCntRes_fromTTCrq signal. When the counter reaches the value of 255 the end_of_frame_pulse_40MHz is issued and the frame_ID_40MHz[15:0] is incremented.These signals are used to drive, respectively, the "end_of_frame_pulse_40MHz" and the "current_event_base_pointer" of the "DRAM_wr_module"
· Event_counter_local: a 24bit counter which is incremented with every new L1Accept_fromTTCrq received. This signal, as well as all that follow, is reset until the DDR2 SDRAM buffer is initialized and it is reset also in response to the BCntRes_fromTTCrq
· Bunch_counter_local: a 12bit counter incremented at every “clk_40MHz” period
· L1Accept_dummy_out: simulated TTC L1Accept which is forwarded to the top level module where it is instantiated the selector between simulated_TTC_signals and true_TTC_signals. In the case of the simulation the TTC_dummy_out signals are feedback to the TTC_signals input at the testbench level (this is true for all the TTC dummy_out signals)
· BCntStrb_dummy_out: simulated TTC BCntStrb
· EvCntHStrb_dummy_out: simulated TTC EvCntHStrb
· EvCntLStrb_dummy_out: simulated TTC EvCntLStrb
· BCntEvCntData_dummy_out: simulated TTC BCntEvCntData; this signal is loaded with:
o “latency_corrected_clk_counter_plusone” when L1Accept_dumy_out and BCntStrb_dummy_out are active; the content of the counter is incremented by 1 w.r.t. the “latency_corrected_clk_counter” so that the BCnt information will match the trigger time stamp produced by the “na62_trig_rqst_buffer” module upon reception of the L1Accept, one clock cycles later
o “Event_counter[11:0]” when EvCntLStrb_dummy_out” is active
o “Event_counter[23:12]” when EvCntHStrb_dummy_out” is active
The generation of simulated triggers in the “na62_trig_rqst_buffer” module is not enabled until the “pause” input becomes unactive and until a number of 40MHz clock cycles greater than TRIG_LAT_IN_CLK_CYCLES (whose active value is assigned in the module “na62_hpcii_driver_vhd” ) has elapsed. Furthermore there is a limit to the number of triggers processed per frame, which is set by the value of the macro NUMBER_OF_TRIGGERS_IN_A_FRAME defined in the “na62_hpcii_driver_vhd” module, currently at 6 (<-> average of about 1MHz trigger rate).
The trigger_fifo_vhd entity instantiated by this module is a simple single clock fifo with the following declaration:
ENTITY trigger_fifo_vhd IS
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (59 DOWNTO 0);
rdreq : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (59 DOWNTO 0);
usedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
END trigger_fifo_vhd;