THE BITSCOPE DESIGN
Browse this part of the website to learn about:
1. What Bitscope is, how it works, and how to use it.
2. The hardware design schematics, fully annotated.
3. How to program Bitscope (including a detailed manual).
4. What parts you need to build a Bitscope.
5. Some free software you can download for Bitscope.
The key features of the BitScope design are:
· Simultaneous analog/digital capture· 100 MHz sub-sampling bandwidth
· 50 Ms/s logic sample rate (max)
· 40 Ms/s analog sample rate (max)
· 20 MHz single-shot bandwidth
· 4 analog inputs (multiplexed)
o 2 inputs via BNC (buffered 1Meg)
o 2 inputs via DB25 POD
· 8 logic inputs via DB25 POD
· Two 32K x 8 capture buffers
· Sophisticated triggers (analog or digital)
· 10 MHz arbitrary waveform generator / · Fully programmable using ASCII "scripts"
· Simple virtual machine programming
· Optional A/D convertor modules
· Expansion POD for external devices
· Low cost PIC 16F628 design
· All logic in a single PLD
· 115 kb/s Serial Interface or
· 625 kb/s 10BaseT Ethernet Interface
· 1.25 Mb/s USB Interface
· "Atomic" ASCII command set
· Scalable design to >100MS/s @ 3.3V
· Chipset suitable for embedded DSO
Hardware Design
This section describes the original hardware. The BS300 design is similar. BS300 schematics are available here.The schematics below describe the main circuit.
The next few pages walk you through the design.
The sub-sections provide details of the analog circuits, A/D convertor and expansion POD. / If you have a PDF reader installed in your web browser, you can click on the thumbnails to see each schematic in detail.
You can also can download all five sheets in one zip file from our download area.
In addition to the main circuit, you can also view the schematics of our high speed A/D convertor.
A/D Convertor
and our new circuit prototyping system called ProtoPOD
Proto POD
which connects to Bitscope's Logic POD connector.
Main Board
Sheet 1 / This is the master Bitscope schematic. All the following sheets show parts of this circuit in greater detail.
Sheet 2 / Power supply and serial interface circuits.
Sheet 3 / Logic Analyzer circuit.
Sheet 4 / Analog inputs, buffers and A/D convertor interface.
Sheet 5 / Vertical input channel buffer amplifiers.
Analog Inputs
The primary source of analog signals is through the CH A and CH B BNC connectors.
These input circuits are designed to be compatible with normal 10:1 CRO probes.
This schematic left shows CH A. CH B is identical.
S1 provides AC/DC coupling via 100nF cap C32 and the 1M resistor to GND provides the nominal 1M input impedance.
R25, C31, D8 and D9 and provide input protection.
The high impedance voltage follower circuit use JFETs Q6 and Q7.
The Opperating point and offset adjust is set by Q3/RV3.
MAXIM to the rescue
JFETs have quite a high output impedance so U23, a unity gain follower, is provided to buffer the analog signal to the next stage.
Of course, this buffer and others that follow it must perform to the highest standards if the integrity of the analog signal is to maintained until it reaches the A/D convertor.
A few years ago, wide bandwidth OP Amps were considered rocket science. Then came the Maxim MAX477. This device has a 300 MHz GBP, uses voltage feedback and is happy to drive 50 ohm capacitive loads. As an added bonus, it has a 1 Meg input impedance and negligible input capacitance.
This is just the ticket for getting a wide bandwidth signal to an A/D convertor.
The analog path to the A/D convertor passes through a series of these wide bandwidth OP amps before being applied to 4:1 analog multiplexer. This combination avoids RC filters which could degrade the high frequency components of our signal.
Logic POD Analog Inputs
The other analog inputs connect via the POD and are attenuated by the 20K network R22 and R23.
The schematic left shows CH B. CH A is identical.
To compensate for the input capacitance of the multiplexer which follows this circuit, an optional speedup capacitor C57 is available. This may need to be trimmed and should have a nominal value of Cin/4 (about 0-10pF).
The maximum input voltage of the range buffer which follow this is ±3V. So given an attenuation factor of 4.830, this means a maximum analog voltage at the POD of ±15V can be measured. This is suitable for most solid state designs. Higher voltage ranges can be accomodated with extra circuitry in the POD itself.
Analog Input Multiplexer
The 4 input buffers feed a MAX4052 MUX to select one of them to pass on to the next stage.
U17 selects the input according to the values of:
(1) PIC pin RA2: CH-A/B select and,
(2) PLD pin PG0: BNC/Pod select.
CH-A/B is under the control of the PIC which can be programmed to chop the source between the pair of BNC inputs or the pair of POD inputs during a trace.
BNC/Pod is set via an option bit in Spock and may only be changed when Spock is reloaded. That is, between traces.
This signal also selects the SRAM bank so we have a completely separate 16K buffer for both Analog and Digital samples for POD and BNC sources !
As a bonus, there is a spare 4:1 MUX in U17 used to activate 1 of 4 front panel LEDs
Channel sample indicators on the front panel such as these are an important feature of modern DSO :-)
They look good and tell you when Bitscope is actually acquiring analog data.
Range Buffer
U14 is a straight 300 MHz unity gain follower that buffers the output of the multiplexer. The low impedance output of this buffer drives the attenuator section. 3 Resistor networks give attenuation of 1, 2 and 5.273. The other option is a x 4.583 gain stage to boost low level signals.
The 4 range options are switched by MUX U18 (4052). This MUX is addressed by RNG0, RNG1 outputs from the PIC.
Depending on the 4052 (MAXIM is best) you may need to add a small speedup cap C69 to the 5:1 range for ideal frequency response. A poor mans trimmer can be made from some adhesive copper foil (stained glass supplier) and a bit of paper.
Gain Buffer
U15 is configured as a (x 4.583) non-inverting amp to boost small signals to feed the ADC. It is possible to use the MAXIM 477 device here, but for a gain of 5 it has only a bandwidth of 25 MHz. The better choice is the Analog devices AD8048 which is optimized for gains of +2 or more.
At a gain of 5, the AD8048 has a bandwidth of better than 50 MHz. For even better performance you may be able to reduce the gain of U15 slightly. The bandwidth improvement will follow 1/[1+Rf/Rg]. The AD8048 has a unity gain mate - the AD8047 - which is virtually a drop in replacement for the MAXIM 477.
If you use the Analog Devices AD9057 ADC (the pick of the litter) which has a 1 V span, you may halve the gain of this stage, preserving the 100MHz bandwidth across all ranges. This is useful, even though the AD9057 samples at 40/60/80 MSPS it has an analog bandwidth of 120MHz! This may seem confusing, but will be explained below. There is a bit more to sampling than you might think.
By the way, because this is a 8 bit sample engine, we don't care too much for whole numbers in the gains. The Host display software can sort this out with high precision arithmetic. All the Host needs to know are the constants for each range for a device. There lies a use for some of the 64 bytes of EEPROM in the PIC16F84!
ADC Buffer
After the range selector the analog signal is buffered and amplified by U16.
This stage has a gain of 1.667 which takes an input clamped at ±0.6v and outputs a ±1.0v signal.
The output offset is set by emitter follower Q5 and RV1. Adjusting RV1 will shift the signal span to match the input of the A/D module being used.
For example:
(1) The Motorola ADC has a 2V span centered at 1V.
(2) The AD9057 has a 1V span centered at 2.5V
(3) The TI TLC5540 has a 2V span centered at 1.62V
Diode clamps on the input to U16 ensure that the input to the ADC never exceeds 2V p-p.
Some ADC chips do not tolerate overvoltage on the input.
Current limiting resistors R38, R29 ensure that the mighty MAXIM drivers do not exceed the current limits of the Range Select multiplexer.
The ADC Buffer provides a low impedance drive for the ADC, which may be a few hundred ohms and 30 pF or so. Note that C27 takes off the AC component of the input to the ADC for edge counting in Spock.
RV2 is connected to pin 24 of the ADC to adjust the span. This allows the span to be calibrated if possible for the particular ADC in use.
A/D Interface
Bitscope's modular A/D interface allows the use of more than one type of A/D convertor.
The interface itself is simple.
The data bus drives the Analog SRAM, Spock and MUX. The sample clock is the same zz-clk used by Spock and !STORE drives the !OE pin.
The "nominal" A/D convertor for Bitscope is the now obsolete Motorola MC10319 "Flash Convertor" which used a comparator tree and gray scale decoder allowing it to be clocked from 25MHz down to DC.
When Bitscope was designed, this A/D convertor was already "on its way out", so why design in an outdated chip ?
Because it's the perfect footprint for a replaceable A/D Module !
The MC10319 was available in a 24pin 600mil package. It used all the analog and digital power supplies, data bus, and control signals as required by any A/D convertor.
Rather than design a new PCB for every different ADC chip on the market (which are all surface mount now anyway) it seemed a better bet to design for the Motorola part, then make a 24pin 600mil "carrier" PCB for each new Flash ADC of interest.
If you examine the spec sheets on a many A/D convertors, you will see they work in much the same way. The only real difference is the input offset and span details.
The module scheme adopted in Bitscope is quite flexible. It is even conceivable that a 16 bit ADC module could be devised that outputs odd/even byte pairs.
PIC Processor
Bitscope is based on the MicroChip PIC 16F84.
The PIC's fast RISC instruction set and the tri-state I/O pins make it ideal for Bitscope.
At first glance you may think that an 18 pin PIC does not have enough pins for a useful design.
However, with careful planning it is possible to use most pins for more than one function which makes good use of the features of this innovative microcontroller while keeping the construction costs down.
The key is to reuse several of the pins depending on the hardware operating mode. In Bitscope's case, two modes are defined; COUNT and SHIFT.
Here is a brief description of the pin functions:
PIN / Function / DescriptionRA0
RA1 / Range 0
Range 1 / COUNT mode:
Output pins that control the Analog gain of the Y amplifiers.
· 0 Gain = 4.583
· 1 Gain = 1.000
· 2 Gain = 0.500
· 3 Gain = 0.190
Note that the gain of the ADC Buffer is 1.667
POD I/O 0
POD I/O 1 / SHIFT mode:
I/O pins that are available at the LOGIC POD for external Smart PODs. In COUNT mode, analog switches isolate these signals from the LOGIC POD.
RA2 / Channel A/B / Output pin that swiches the Analog source between CHA BNC and CHB BNC, or in POD mode between PODA or PODB analog signals brought from the LOGIC POD.
RA3 / zz-clk / "The clock that sleeps". Tri-state I/O pin. State machines in PLD devices should not be exposed to glitches on the clock. Some registers may see the clock, others may may not, resulting in non-deterministic behavior. Jamming a 50MHz clock signal is not polite. U6A (74AC74) is double clocked by frequency doubler U3D (74AC86) (on the clean edge) and allows the PIC to have 3 state synchronous control via RA3. High, Low, Freerunning - no glitches. This control is important as we must use zz-clk to shift in control words to the PLD as well as modulate the sampling for lower frequency timebase measurements.
RA4 / Digital Data / Input connects to U5 8:1 MUX to read the 8 data bits of the Logic Analyzer RAM bus. Bit7 is routed through Spock to be optionally the TRIGGER MATCH or FREQUENCY/EVENT signals. RA4 may be connected to the PIC prescaler in the OPTION register
RB0 / Analog Data / COUNT mode:
Input connects to U4 8:1 MUX to read the 8 data bits of the ADC RAM Bus. As RB0 is the PIC INT source, during SAMPLE, if the MUX points to Bit7 then INT may be used as a zero crossing detector for Analog TRIGGER (in additional to the Complex trigger implemented in the PLD)
Spock Data In / SHIFT mode:
Output signal is Shift-In data to feed Spock which needs 5 bytes to set up counters, trigger bytes and options.
RB1 / SEL 0 / COUNT mode:
Output A0 for data MUXs U4, U5.
Spock Data Out / SHIFT mode:
Input Shift-Out data from Spock. Current 16 bit counter state in Spock is shifted out as new data is shifted in.
RB2
RB3 / SEL 1
SEL 2 / Output pins A1, A2 for data MUXs U4, U5.
RB4 / COUNT/!SHIFT / Output which controls the hardware mode. That is, COUNT or SHIFT. A value of ONE causes Spock to shift new data into its registers. A value of zero causes Spock to count and trigger.
RB5 / Serial Out / Serial data output.
RB6 / Serial In / Serial data Input.
RB7 / STORE/!READ / Output control for RAM and ADC/Buffer control. This signal selects either read or write for the RAM, allowing SAMPLE data written to RAM, or later read back.
CLKI
CLKO / Clock Select / The PIC is clocked by a crystal - which depending on the PIC device may be 4MHz, 10 MHz or 20MHz
Spock PLD