RFA Form RFA # 1
Request For Action Form
LRO CRaTER Instrument Electronics
Critical Design Review
At GSFC
22 May 2006
Originator Name: Jose Florez Phone #: 301-286-3594 Org: GSFC 560
RFA Title: FPGA Output Staggering
Action:
It is recommended that the outputs be staggered in time over the 4 quadrants of the part to prevent internal ground bounce.
Rationale:
Based on experience with several GSFC programs.
Chairman/PDL Acceptance/Clarification:
Assigned To: Assignee Phone #
Date Closed:
RFA Response RFA # 1
LRO CRaTER Instrument Electronics Critical Design Review
RFA Title: FPGA Output Staggering Date:
Assigned To: Phone #:
Response:
We will look at the FPGA I/O and ground characteristics on the Engineering Unit. If there is significant noise and/or ground bounce, we will consider the following:
1. Staggering (in time) the switching of outputs that are grouped in a bank.
2. Reassignment of I/O pins if necessary.
3. Improved decoupling.
Additional Information Needed From Goddard:
RFA Impact on Cost/Schedule/Risk:
RFA Form RFA # 2
Request For Action Form
LRO CRaTER Instrument Electronics
Critical Design Review
At GSFC
22 May 2006
Originator Name: Jose Florez Phone #: 301-286-3594 Org: GSFC 560
RFA Title: Signal Integrity Analysis
Action:
Perform signal integrity analysis of all FPGA I?O lines to assess the need for termination resistors. If analysis is not performed the resistors should be added to every single line.
Rationale:
Based on experience with SDO program. The SX 72 package output impedance is reactive and will oscillate every time a pulse leaves the package.
Chairman/PDL Acceptance/Clarification:
Assigned To: Assignee Phone #
Date Closed:
RFA Response RFA # 2
LRO CRaTER Instrument Electronics Critical Design Review
RFA Title: Signal Integrity Analysis Date:
Assigned To: Phone #:
Response:
We will look at the FPGA I/Os on the Engineering Unit, checking for overshoot and undershoot. If more series resistors are required, they will be added when we move to the flight layout.
Additional Information Needed From Goddard:
RFA Impact on Cost/Schedule/Risk:
RFA Form RFA # 3
Request For Action Form
LRO CRaTER Instrument Electronics
Critical Design Review
At GSFC
22 May 2006
Originator Name: Jose Florez Phone #: 301-286-3594 Org: GSFC 560
RFA Title: Radiation Performance of Electronic Parts
Action:
Perform analysis to determine the number of SEU hits the electronics are expected to receive relative to those detected by the telescope. Is ther a requirement?
Rationale:
The instrument electronics should not be a significant limiting factor to the science objectives.
Chairman/PDL Acceptance/Clarification:
Assigned To: Assignee Phone #
Date Closed:
RFA Response RFA # 3
LRO CRaTER Instrument Electronics Critical Design Review
RFA Title: Radiation Performance of Electronic Parts Date: 5/31/06
Assigned To: Bob Goeke Phone #: 617-253-1910
Response:
There is not s direct requirement for SEU effects on the circuitry, but – in the absence of test data on the analog parts – a /very/ worst case calculation can be made. If /every particle which transited a chip in the signal chain caused a system response which /looked/ like a real signal, then the false event rate would simply be the ratio of the area of the silicon chips in the components to the area of our silicon detector. This ratio turns out to be
30 : 1000 (the areas are in square mm)
So we have a maximum “background” processing rate increase of 3%. Since scientifically interesting events are required to exhibit coincidence in at least two separate signal chains, these SEU events do not affect the downlinked science rate at all.
Additional Information Needed From Goddard:
RFA Impact on Cost/Schedule/Risk:
RFA Form RFA # 4
Request For Action Form
LRO CRaTER Instrument Electronics
Critical Design Review
At GSFC
22 May 2006
Originator Name: Jose Florez Phone #: 301-286-3594 Org: GSFC 560
RFA Title: Independent Review of FPGA Design
Action:
It is recommended that an independent review of the FPGA internal design be conducted.
Rationale:
To verify that sufficient analysis has been performed to guarantee the part will meet mission requirements over the temperature range and at the EOL.
Chairman/PDL Acceptance/Clarification:
Assigned To: Assignee Phone #
Date Closed:
RFA Response RFA # 4
LRO CRaTER Instrument Electronics Critical Design Review
RFA Title: Independent Review of FPGA Design Date:
Assigned To: Phone #:
Response:
We will consult with the Project on how this might be best accomplished within our current resource constraints.
Additional Information Needed From Goddard:
RFA Impact on Cost/Schedule/Risk:
RFA Form RFA # 5
Request For Action Form
LRO CRaTER Instrument Electronics
Critical Design Review
At GSFC
22 May 2006
Originator Name: Tom Winkert Phone #: 301-286-2917 Org: GSFC 561
RFA Title: SSO (Simultaneous Switching Outputs)
Action:
Review SSO scheme, specifically SRAM ADR and DATA.
Rationale:
Large bus switching can cause unwanted glitches.
Chairman/PDL Acceptance/Clarification:
Assigned To: Assignee Phone #
Date Closed:
RFA Response RFA # 5
LRO CRaTER Instrument Electronics Critical Design Review
RFA Title: SSO (Simultaneous Switching Outputs) Date:
Assigned To: Phone #:
Response:
We will look at the FPGA I/O and ground characteristics on the Engineering Unit. If there are SSO effects we will consider staggering the switching of outputs that are grouped in a bank or reassigning pins if necessary.
Additional Information Needed From Goddard:
RFA Impact on Cost/Schedule/Risk:
RFA Form RFA # 6
Request For Action Form
LRO CRaTER Instrument Electronics
Critical Design Review
At GSFC
22 May 2006
Originator Name: Tom Winkert Phone #: 301-286-2917 Org: GSFC 561
RFA Title: HCS to ACS Compatibility
Action:
Verify the HCS14 edge rate is fast enough to drive aCS74 input.
Rationale:
Some digital devices have minimum edge rate inputs.
Chairman/PDL Acceptance/Clarification:
Assigned To: Assignee Phone #
Date Closed:
RFA Response RFA # 6
LRO CRaTER Instrument Electronics Critical Design Review
RFA Title: HCS to ACS Compatibility Date: 6/2/06
Assigned To: Bill Crain Phone #: 310-336-8530
Response: We will switch the part to a 54AC14 (which we use elsewhere!).
Additional Information Needed From Goddard:
RFA Impact on Cost/Schedule/Risk:
RFA Form RFA # 7
Request For Action Form
LRO CRaTER Instrument Electronics
Critical Design Review
At GSFC
22 May 2006
Originator Name: Tom Winkert Phone #: 301-286-2917 Org: GSFC 561
RFA Title: Actel I/O Editor
Action:
Fix pin 181 in Actel I/O editor.
Rationale:
The Actel Designer tool can change the pin numbers if they are not fixed.
Chairman/PDL Acceptance/Clarification:
Assigned To: Assignee Phone #
Date Closed:
RFA Response RFA # 7
LRO CRaTER Instrument Electronics Critical Design Review
RFA Title: Actel I/O Editor Date:
Assigned To: Phone #:
Response:
This has been done.
Additional Information Needed From Goddard:
RFA Impact on Cost/Schedule/Risk:
RFA Form RFA # 8
Request For Action Form
LRO CRaTER Instrument Electronics
Critical Design Review
At GSFC
22 May 2006
Originator Name: Tom Winkert Phone #: 301-286-2917 Org: GSFC 561
RFA Title: Actel Timing Analysis
Action:
Set timing constraints for:
1) Register to Register
2) Input to Register
3) Register to Output
4) Input to Output
Rationale:
Putting timing constraints up-front makes timing verification easier.
Chairman/PDL Acceptance/Clarification:
Assigned To: Assignee Phone #
Date Closed:
RFA Response RFA # 8
LRO CRaTER Instrument Electronics Critical Design Review
RFA Title: Actel Timing Analysis Date:
Assigned To: Phone #:
Response:
The frequency of this design (16MHz Master clock) is not demanding compared to the capability of the Actel SX72 family. Hence, the only pre-route constraint used for this design is: system clock frequency must be >= 20MHz. (This constraint has been set at the synthesizer stage, which passes an EDIF netlist of Actel primitives to the Designer Software.) Post-route, clock frequency is re-verified and longest/shortest paths are checked with the Actel Static Timing Verifier. Dynamic (worst-case backannotated) simulation is also performed.
Additional Information Needed From Goddard:
RFA Impact on Cost/Schedule/Risk:
RFA Form RFA # 9
Request For Action Form
LRO CRaTER Instrument Electronics
Critical Design Review
At GSFC
22 May 2006
Originator Name: Tom Winkert Phone #: 301-286-2917 Org: GSFC 561
RFA Title: Async Reset 1
Action:
Review Async Reset 1.
Rationale:
Making Reset 1 synchronous will make timing verification easier.
Chairman/PDL Acceptance/Clarification:
Assigned To: Assignee Phone #
Date Closed:
RFA Response RFA # 9
LRO CRaTER Instrument Electronics Critical Design Review
RFA Title: Async Reset 1 Date:
Assigned To: Phone #:
Response:
The Actel Static Timer will be used to verify these paths.
Additional Information Needed From Goddard:
RFA Impact on Cost/Schedule/Risk:
RFA Form RFA # 10
Request For Action Form
LRO CRaTER Instrument Electronics
Critical Design Review
At GSFC
22 May 2006
Originator Name: Tom Winkert Phone #: 301-286-2917 Org: GSFC 561
RFA Title: Programming Adapter
Action:
Verify flight programming socket adapter is ESD safe.
Rationale:
In the last year, Actel discovered an ESD problem and have made new sockets.
Chairman/PDL Acceptance/Clarification:
Assigned To: Assignee Phone #
Date Closed:
RFA Response RFA # 10
LRO CRaTER Instrument Electronics Critical Design Review
RFA Title: Programming Adapter Date:
Assigned To: Phone #:
Response:
Our Silicon Sculptor and adapters were purchased in February of 2006. We will check with Actel regarding this problem and upgrade if necessary.
Additional Information Needed From Goddard:
RFA Impact on Cost/Schedule/Risk:
RFA Form RFA # 11
Request For Action Form
LRO CRaTER Instrument Electronics
Critical Design Review
At GSFC
22 May 2006
Originator Name: Tom Winkert Phone #: 301-286-2917 Org: GSFC 561
RFA Title: Bus Ordering
Action:
Verify bus ordering of Actel vs board is OK for RAM and Gate.
Rationale:
It appears the ordering of those busses does not match Actel Database ordering.
Chairman/PDL Acceptance/Clarification:
Assigned To: Assignee Phone #
Date Closed:
RFA Response RFA # 11
LRO CRaTER Instrument Electronics Critical Design Review
RFA Title: Bus Ordering Date:
Assigned To: Phone #:
Response:
The schematic used during the review was not the most current. Since its issue, the analog slices had been re-ordered and several redundant FPGA outputs combined. The FPGA database reflected the modified design. The FPGA pinout has been checked against the current schematic and netlist.
Additional Information Needed From Goddard:
RFA Impact on Cost/Schedule/Risk:
RFA Form RFA # 12
Request For Action Form
LRO CRaTER Instrument Electronics
Critical Design Review
At GSFC
22 May 2006
Originator Name: Jack Shue Phone #: 301-286-5752 Org: GSFC 563
RFA Title: EMI Filter
Action:
Look at putting in a second ATH461 filter. Currently using 1 filter for 2 converters.
Rationale:
Use of 1 filter on multiple converters can cause instability. Also long leads on EMI filters negates filtering. Leads must be less than 1 inch max.
Chairman/PDL Acceptance/Clarification:
Assigned To: Assignee Phone #
Date Closed:
RFA Response RFA # 12
LRO CRaTER Instrument Electronics Critical Design Review
RFA Title: EMI Filter Date: 6/1/06
Assigned To: Bob Goeke Phone #: 617-253-1910
Response:
Although the vendor assures us that a single EMI filter is adequate in our configuration, we will investigate the performance in our engineering unit.
Additional Information Needed From Goddard:
RFA Impact on Cost/Schedule/Risk:
RFA Form RFA # 13
Request For Action Form
LRO CRaTER Instrument Electronics
Critical Design Review
At GSFC
22 May 2006
Originator Name: Jack Shue Phone #: 301-286-5752 Org: GSFC 563
RFA Title: Under-Powered Converters
Action:
Evaluate effects of under-powered converters, I.E. stability problems and extra noise, also balance on converter.
Rationale:
Converters can lose stability at low power levels.
Chairman/PDL Acceptance/Clarification:
Assigned To: Assignee Phone #
Date Closed:
RFA Response RFA # 13
LRO CRaTER Instrument Electronics Critical Design Review
RFA Title: Under-Powered Converters Date: 6/1/06
Assigned To: Bob Goeke Phone #: 617-253-1910
Response:
We will evaluate performance on our Engineering Unit. Although it is now clear that we could drop back from a 12W dual converter to a 5W dual converter, the 12W unit comes with common mode filtering on the output built in (see RFA 14), and so offers some advantage over the 5W unit.
Discussions with the vendor re: running the converters at low load levels indicate that our current design should have adequate margin – but we can easily change to the lower wattage unit if required.
Additional Information Needed From Goddard:
RFA Impact on Cost/Schedule/Risk:
RFA Form RFA # 14
Request For Action Form
LRO CRaTER Instrument Electronics
Critical Design Review
At GSFC
22 May 2006
Originator Name: Jack Shue Phone #: 301-286-5752 Org: GSFC 563
RFA Title: Common Mode Chokes.
Action:
Evaluate need for common mode chokes on all outputs.
Rationale:
Need for noise control.
Chairman/PDL Acceptance/Clarification:
Assigned To: Assignee Phone #
Date Closed:
RFA Response RFA # 14
LRO CRaTER Instrument Electronics Critical Design Review
RFA Title: Common Mode Chokes Date: 6/1/06
Assigned To: Bob Goeke Phone #: 617-253-1910
Response:
We will look carefully at the noise levels on the Engineering Unit and add CM chokes if required (see also response to RFA 13).
Additional Information Needed From Goddard:
RFA Impact on Cost/Schedule/Risk:
RFA Form RFA # 15
Request For Action Form
LRO CRaTER Instrument Electronics
Critical Design Review
At GSFC
22 May 2006
Originator Name: Terry Smith Phone #: 301-286-0651 Org: GSFC 561
RFA Title: Only 1 VCC Pin +5V Power Input On J1 Connecter.
Action:
Look into adding 1 more VCC line (pin) on the J1 connector.
Rationale:
Reliability concern should the 1 pin fail open.
Chairman/PDL Acceptance/Clarification: