EE4271 VLSI Design
In-Class Quiz 6
Name:
- Design a cell library based IC according to the following truth-table specification.
In the system, there are two bit inputs, denoted by A and B, and two bit outputs, denoted by X and Y.
A / B / X / Y0 / 0 / 1 / 1
0 / 1 / 1 / 0
1 / 0 / 0 / 0
1 / 1 / 0 / 1
(a)Use Karnaugh map to get the reduced expression of X and Y using A and B
(b)Using AND, OR and NOT gates to implement the above system
(c)Use technology mapping to map the above circuit to the circuit with NOT and 2-input NAND gates only.
(d) Implement the above circuit using CMOS transistors.
(e)Perform the timing evaluation to the circuit obtained in (c). Assume that each NOT gate has driving resistance of 1 and input capacitance of 1, and each NAND gate has driving resistance of 2 and input capacitance of 2. For simplicity, in this problem, interconnect delay is ignored. In addition, for all the gates with unknown upstream or downstream gates, assume that the unknown gates have 0 driving resistance and 0 input capacitance. What is the delay for the whole combinational circuit?
2. For the same specification, design an IC using full-custom design methodology. Indicate the advantage and disadvantage compared to the cell-library based design.
3.For the same system, implement it using programmable logic array. Indicate the advantage of using programmable logic array.
4. Suppose that unit wire capacitance is 1 and unit wire resistance is 1. Assuming that the arrival time at the primary input gate is 0, compute the arrival time at each gate.
5.Analyze the following circuit with transmission gates and NOT gates. What is the value of Q when C=1? What is the value of Q when C=0?