Application-Dependent Testing of FPGA-Based Circuits

Testing FPGAs and related topics

REFERENCES

FPGAs

[Chen92] K.-C. Chen et al., "Graph-Based FPGA Technology Mapping for Delay Optimization", IEEE Design & Test of Computers, pp. 7-20, Sept. 1992.

[CMSH96] S.-C. Chang, M. Marek-Sadowska, TT. Hwang, "Technology Mapping for TLU FPGA's Based on Decomposition of Binary Decision Diagrams", IEEE Trans. on CAD, pp. 1126-1236, Oct. 1996.

[CoDi96] J. Cong, Y. Ding, "Combinational Logic Synthesis for LUT Based Field Programmable Gate Arrays," ACM Trans. on Design Automation of Electronic Systems, pp. 145-204, Apr. 1996.

[CoDi94] J. Cong, Y. Ding, "FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs”, IEEE Trans. on CAD, pp. 1-12, Jan. 1994.

[HOIW94] T.-T. Hwang, R. M. Owens, M. J. Irwin, K. H. Wang, "Logic Synthesis for Programmable Logic Arrays," IEEE Trans. on CAD, pp. 1280-1287, Oct. 1994.

[LeSa95] V. V. Le, G. Saucier, "A Performance Driven Look-Up Table Mapping," Proc. IFIP Workshop on Logic and Architecture Synthesis, pp. 86-93, 1995.

[LPPV93] Y. T. Lai, K. R. Pan, M. Pedram, S. Vrudhula, "FGMap: A Technology Mapping Algorithm for Lookup Table Type FPGA Synthesis", Proc. 30-th Design Automation Conf., pp. 642-647, 1993.

[LKJK91] T. Łuba, J. Kalinowski, K. Jasiński, A. Kraśniewski, "Combining Serial Decomposition with Topological Partitioning for Effective Multi-Level PLA Implementations", in P. Michel, G. Saucier (Ed.), Logic and Architecture Synthesis, pp. 243-252, Elsevier Science Publishers B. V. (North Holland), 1991.

[LSNK95] T. Luba, H. Selvaraj, M. Nowicka, A. Krasniewski, "Balanced Multilevel Decomposition and Its Applications in FPGA-based Synthesis", in Novel Approaches in Logic and Architecture Synthesis, pp. 109-115, Chapman and Hall, 1995.

[Luba94] T. Luba, "Multi-Level Logic Synthesis Based on Decomposition", Microprocessors and Microsystems, vol. 18, pp. 429-437, Oct. 1994

[LySt96] P. Lysaght, J. Stockwood, "A Simulation Tool for Dynamically Reconfigurable Field Programmable Gate Arrays", IEEE Trans. on VLSI Systems, pp. 381-390, Sept. 1996.

[SCKL93] H. Selvaraj, A. Czerczak, A. Krasniewski, T. Luba, "A Generalized Decomposition of Boolean Functions and Its Applications in FPGA-based Synthesis," Proc. IFIP Workshop on Logic and Architecture Synthesis, pp. 147-166, 1993.

[Schl93] U. Schlichtman, "Boolean Matching and Disjoint Decomposition for FPGA Technology Mapping", Proc. IFIP Workshop on Logic and Architecture Synthesis, pp. 83-102, 1993.

[ShKi95] H. Shin, C. Kim, "Performance-Oriented Technology Mapping for LUT-Based FPGA's", IEEE Trans. on VLSI Systems, pp. 323-327, June 1995.

[Sica91] P. Sicard et al., "Automatic Synthesis of Boolean Functions on Xilinx and Actel Programmable Devices", Proc. EuroASIC'91, pp. 142-145, 1991.

[WaPe92] W. Wan, M. A. Perkowski, "A New Approach to the Decomposition of Incompletely Specifies Multi-Output Function Based on Graph Coloring and Local Transformations and Its Applications to FPGA Mapping", Proc. European Design Automation Conf., pp. 230-235, 1992.

FPGA Testing

[AbSt95] M. Abramovici, C. Stroud, "No-Overhead BIST for FPGAs," Proc. IEEE Int. On-Line Testing Workshop, pp. 90-92, 1995.

[AbSt96] M. Abramovici, C. Stroud, "ILA BIST for FPGAs: A Free Lunch with Gourmet Food," Proc. IEEE Int. On-Line Testing Workshop, pp. 91-94, 1996.

[ALSU97] M. Abramovici, E. Lee, C. Stroud, M. Underwood, "Self-test for FPGAs and CPLDs requires no overhead," EDN, Nov. 6, 1997.

[AbLS??] M. Abramovici, E. Lee, C. Stroud, "BIST-Based Diagnostics of FPGA Logic Blocks", Proc. ???, pp. 196-201, ???.

[AnKr96] R. Antoniewicz, A. Kraśniewski, "Extension of Incompletely Specified Boolean Functions for Synthesis of Testable Circuits Implemented with FPGAs/CPLDs", Proc. EDCC-2 Companion Workshop on Dependable Computing, pp. 121-130, 1996.

[AnKr98] R. Antoniewicz, A. Kraśniewski, "Testability measures for decomposed structures intended for FPGA implementation", Proc. International Conf. on Programmable Devices and Systems, pp. 107-114, 1998.

[Anto98] R. Antoniewicz, "Comparison of Testability Properties of Logic Networks Obtained by Serial Disjoint Decomposition", Proc. Design and Diagnostics of Electronic Circuits and Systems Workshop, 1998.

[BiKr98] J. Binda, A. Kraśniewski, "Testing Complex Circuits Implemented Using In-System Programmable Devices", Proc. 9th European Workshop on Dependable Computing, pp. 50-53, 1998.

[BuLa97] A. L. Burress, P. K. Lala, "Logic Design for Self-Testing FPGA Implementation", Proc. 3rd On-Line Testing Workshop, pp. 207-211, 1997.

[HaDu98] F. Hanchek, S. Dutt, "Methodologies for Tolerating Cell and Interconnect Faults in FPGAs", IEEE Trans. on Computers, pp. 15-33, Jan. 1998.

[HuLo96] W. K. Huang, F. Lombardi, "An Approach for Testing Programmable/ Configurable Field Programmable Gate Arrays", Proc. 14th VLSI Test Symp., pp. 450-455, 1996.

[HMCL98] W. K. Huang, F. J. Meyer, X.-T. Chen, F. Lombardi, "Testing Configurable LUT-Based FPGA's", IEEE Trans. on VLSI Systems, pp. 276-283, June 1998.

[InMF98] T. Inoue, S. Miyazaki, H. Fujiwara, "Universal Fault Diagnosis for Lookup Table FPGAs", IEEE Design & Test of Computers, pp. 39-44, Jan.-March 1998.

[ItMK97] N. Itazaki, Y. Matsumoto, K. Kinoshita, "BIST for PLBs of a Look-Up Table Type FPGA - A Comparator Based BIST Technique under Definite Fault Model", Proc. 3rd On-Line Testing Workshop, pp. 202-206, 1997.

[JoMa93] C. Jordan, W. P. Marnane, "Incoming Inspection of FPGAs", Proc. European Test Conf. pp. 371-377, 1993.

-[KeIv94] J. L. Kelly, P. A. Ivey, "Defect Tolerant SRAM-Based FPGAs", Proc. IEEE Int'l Conf. on Computer Design, pp. 479-482, 1994.

[KrNL95] A. Kraśniewski, M. Nowicka, T. Łuba, "Pseudoexhaustive Testability of Circuits Designed for FPGA/CPLD Implementation," Proc. IFIP Workshop on Logic and Architecture Synthesis, pp. 319-329, 1995.

[KrNo96] A. Kraśniewski, M. Nowicka "Application-Dependent Testability of FPGA-Based Circuits Designed Using Functional Decomposition," Proc. IFIP Workshop on Logic and Architecture Synthesis, pp. 167-175, 1996.

[Kras97] A. Kraśniewski, "Design for Application-Dependent Testability of FPGAs," Proc. Int'l Workshop on Logic and Architecture Synthesis, pp. 245-254, 1997.

[LACH96] F. Lombardi, D. Ashen, X. Chen, W. K. Huang, "Diagnosing Programmable Interconnect Systems for FPGAs", Proc. ACM/SIGDA Int'l Symp. on FPGAs, pp. xxx, 1996.

[ReFZ97] M. Renovell, J. Figueras, Y. Zorian, "Test of RAM-based FPGA: Methodology and Application to the Interconnect", Proc. 15th VLSI Test Symp., pp. 230-237, 1997.

[RPFZ98] M. Renovell, J. M. Portal, J. Figueras, Y. Zorian, "Testing the Interconnect of RAM-Based FPGA ", IEEE Design & Test of Computers, pp. 45-50, Jan.-March 1998.

[SCKA96] C. Stroud, P. Chen, S. Konala, M. Abramovici, "Evaluation of FPGA Resources for Built-In Self-Test of Programmable Logic Blocks", Proc. ACM/SIGDA Int'l Symp. on FPGAs, pp. 107-113, 1996.

[SKCA96] C. Stroud, S. Konala, P. Chen, M. Abramovici, "Built-In Self-Test of Logic Blocks in FPGAs (Finally, a Free Lunch: BIST Without Overhead!)", Proc. 14th VLSI Test Symp., pp. 387-392, 1996.

-[Stro96] C. Stroud et al., "Using ILA Testing for BIST in FPGAs", Proc. IEEE Int'l Test Conf., pp. 68-75?, 1996.

[StLA97] C. Stroud, E. Lee, M. Abramovici, "BIST-Based Diagnostics of FPGA Logic Blocks", Proc. IEEE Int'l Test Conf., pp. 539-547??, 1997.

[SWHA98] C. Stroud, S. Wijesuriya, C. Hamilton, M. Abramovici, "Built-In Self-Test of FPGA Interconnect", Proc. IEEE Int'l Test Conf., 1998.

[ShMP98] N. R. Shnidman, W. H. Mangione-Smith, M. Potkonjak, "On-Line Fault Detection for Bus-Based Field Programmable Gate Arrays”, IEEE Trans. on VLSI Systems, pp. 656-666, Dec. 1998.

[ToKr98a] P. Tomaszewicz, A. Kraśniewski, "Functionally exhaustive self-testing of in-system reconfigurable FPGA devices", Proc. Int'l Conf. on Programmable Devices and Systems, pp. 233-238, 1998.

[ToKr98b] P. Tomaszewicz, A. Kraśniewski, "Samotestowanie rekonfigurowalnych układów FPGA zaprogramowanych przez użytkownika", Materiały Krajowego Symp. Telekomunikacji, tom B, str. 126-132, 1998.

[ToKr99] P. Tomaszewicz, A. Kraśniewski: “Self-testing of s-compatible test units in user-programmed FPGAs”, Proc. Of the 25th EUROMICRO Conf., vol. I, pp. 254-259, 1999.

[WaTs97] S.-J. Wang, T.-M. Tsai, "Test and Diagnosis of Faulty Blocks in FPGAs", Proc. IEEE/ACM Int'l Conf. on CAD, pp. 722-727, 1997.

[ZhWL98] L. Zhao, D. M. H. Walker, F. Lombardi, "IDDQ Testing of Bridging Faults in Logic Resources of Reconfigurable Field Programmable Gate Arrays", IEEE Trans. on Computers, pp. 1136-1152, Oct. 1998.

Pseudoexhaustive Testing

[Aker85] S. B. Akers, "On the Use of Linear Sums in Exhaustive Testing", Proc. 15-th Symp. on Fault-Tolerant Computing, pp. 148-153, 1985.

[Kras95] A. Krasniewski, Verification Testing Oriented Decomposition of Boolean Functions, Technical Report, Institute of Telecommunications, Warsaw Univ. of Technology, Aug. 1995.

[Kras86] A. Krasniewski, "Automatic Design of Exhaustively Self-Testing VLSI Circuits", Proc. 12-th European Solid-State Circuits Conf., pp. 167-169, 1986.

[Kras90] A. Kraśniewski, "Design for Verification Testability", Proc. European Design Automation Conf., pp. 644-648, 1990.

[MuKr91] W. Murzyn, A. Kraśniewski, "Integrating Verification Testing and Logic Synthesis", Proc. EuroASIC'91, pp. 322-326, 1991.

[Kras91] A. Kraśniewski, "Logic Synthesis for Efficient Pseudoexhaustive Testability", Proc. 28-th ACM/IEEE Design Automation Conf., pp. 66-72, 1991.

[McCl84] E. J. McCluskey, "Verification Testing - A Pseudoexhaustive Test Technique", IEEE Trans. on Computers, vol. C-33, pp. 541-546, June 1984.

CSTP

[PiKK92] S. Pilarski, A. Kraśniewski, T. Kameda, "Estimating Testing Effectiveness of the Circular Self-Test Path Technique", IEEE Trans. on CAD, pp. 1301-1316, Oct. 1992.

Delay Faults

[KrWr94] Kraśniewski, L. B. Wroński, "Coverage of Delay Faults: When 13% and 99% Mean the Same," in K. Echtle, D. Hammer, D. Powell (Eds.), Dependable Computing - EDCC-1, Lecture Notes in Computer Science, 852, pp. 178-195, Springer Verlag, 1994.

[Kras97] A. Kraśniewski, "Coverage of Delay Faults: Single Number Can Be Very Misleading," Int'l Journal of Computer Systems Science & Engineering, pp. 3-12, Jan. 1997.

[KrCh96] A. Krstic, K.-T. Cheng, "Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability", Proc. European Design & Test Conf., 1996.

TPGs for Delay Faults

[ChGu96a] C.-A. Chen, S. K. Gupta, "BIST Test Pattern Generators for Two-Pattern Testing - Theory and Design Algorithms", IEEE Trans. on Computers, pp. 257-269, March 1996.

[ChGu96b] C.-A. Chen, S. K. Gupta, "Design of Efficient BIST Test Pattern Generators for Delay Testing", IEEE Trans. on CAD, pp. 1568-1575, Dec. 1996.

[CrKi85] G. L. Craig, C. R. Kime, "Pseudo-Exhaustive Adjacency Testing: A BIST Approach for Stuck-Open Faults", Proc. IEEE Int'l Test Conf., pp. 126-137, 1985.

[DuZo97] C. Dufaza, Y. Zorian, "On the Generation of Pseudo-Deterministic Two-Patterns Test Sequence with LFSRs", Proc. European Design & Test Conf., 1997.

[PiPi93] S. Pilarski, A. Pierzynska, "BIST and Delay Fault Detection", Proc. IEEE Int'l Test Conf., pp. 236-242, 1993.

[Star84] C. W. Starke, "Built-In Test for CMOS Circuit", Proc. IEEE Int'l Test Conf., pp. 309-314, 1984.

[ZhBM92] S. Zhang, R. Byrne, D. M. Miller, "BIST Generators for Sequential Faults", Proc. IEEE Int'l Conf. on Computer Design, pp. 260-263, 1992.

Insertion of BIST registers

[Kras86] A. Krasniewski, "Automatic Design of Exhaustively Self-Testing VLSI Circuits", Proc. 12-th European Solid-State Circuits Conf., pp. 167-169, 1986.

[KrAl85a] A. Kraśniewski, A. Albicki, "Self-Testing Pipelines", Proc. IEEE International Conf. on Computer Design: VLSI in Computers, pp. 702-706, 1985.

[KrAl85b] A. Kraśniewski, A. Albicki, "Automatic Design of Exhaustively Self-Testing Chips with BILBO Modules", Proc. IEEE Int'l Test Conf., pp. 362-371, 1985.

Testing - General Issues

[AgKS93] V. D. Agrawal, C. R. Kime, K. K. Saluja, "A Tutorial on Built-In Self-Test, Part 2: Applications", IEEE Design & Test of Computers, pp. 69-77, June 1993.

[Park92] K. P. Parker, The Boundary-Scan Handbook, Kluwer Academic Publ., 1992.

[Kras96] A. Kraśniewski, "Design of Dependable Hardware: What BIST Is Most Efficient," in A Hławiczka, J. G. Silva, L. Simoncini (Eds.), Dependable Computing - EDCC-2, Lecture Notes in Computer Science, 1150, pp. 233-245, Springer Verlag, 1996.

Logic synthesis and functional decomposition

[Bray87] R. K. Brayton, "Algorithms for Multi-Level Logic Synthesis and Optimization", in G. De Micheli, A. Sangiovanni-Vincentelli, P. Antognetti (ed.), Design Systems for VLSI Circuits, Martinus Nijhoff Publ., 1987.

[LaPP96] Y.-T. Lai, K.-R. R. Pan, M. Pedram, "OBDD-Based Function Decomposition: Algorithms and Implementation", IEEE Trans. CAD, pp. 977-990, Aug. 1996.

[Sasa93] T. Sasao, Logic Synthesis and Optimization, Kluwer Academic Publ., 1993.

[WuEA95] B. Wurth, K. Eckl, K. Antreich, "Functional Multiple-Output Decomposition: Theory and an Implicit Algorithm", Proc. 32-nd Design Automation Conf., pp. 54-59, San Francisco, 1995.

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