RONALD DIETZSECRET/SBI CLEARANCE
7102 S. Davies St.
Littleton, Co. 80120-3528
PERSONAL:
Birth date:10/10/49Married5'6''185 lbs.U. S. Citizen
EDUCATION:
UNIVERSITY OF PITTSBURGH, Pittsburgh, Pa.
1972M. A. EducationGPA: 3.5 of 4.0
1971B. S. PhysicsGPA: 2.94 of 4.0
MISC:Additional Training:Zuken/Zuken Lightning, Mentor graphics/Hyperlynx/HDL Designer/Modelsim, Robotics; IBM PC Hardware;; Microcomputers;; High speed-high density Data Rate Recorders, Managing Personal Growth; Outward Bound, Actel and Xilinx FPGA Training Courses, DSP, I maintain my designs in FPGA and circuit Board design by attending weekly FPGA design seminars and other vendor seminars
Software Languages:Basic, Assembly, Pascal, Introduction to C & Unix;
Hardware:8085, Z80, 8086, 8051, MC68HC11, R3000/1, 1750A/B, ADSP21060, Actel and Xilinx FPGAs
BUSINESS
EXPERIENCE:
1/80 to LOCKHEED MARTIN, Denver, Co.
PresentStaff Engineer
Responsible for microprocessor/High Speed digital circuit/DSP design and test. Experienced with the 80C85, Z80, 80C86, MC68HC11, 80C51, and R3000/1 1750A/B, and ADSP21060 microprocessors/microcontrollers. Experienced in Radiation Hard, seu immune design for deep space science instruments. Experienced in Actel and Xilinx FPGA and PWB designs.
InSight program (11/12 to present) I have completedan RTAX 2000 FPGA design with a NOR and NAND flash memory controller and a UHF I/F. I am also the FPGA and verification lead and Uplink Downlink board CPE.
Goes-Rprogram (01/5/10 to 11/12)
Design/Analyze and test the SpaceWire Routing card. This design has two BAE SpaceWire ASICs and RTAX2000 FPGAs. The SK and EDU boards use reprogrammable Actel ProASIC3E FPGAs on Actel prototyping adapters.
Grail program (10/07/08 to 05/28/10)
Modified and test my MRO ULDL Board.
Designed, simulated and tested a flash memory controller for the MPIC ASYN FPGA using an Actel RTAX2000 FPGA
JUNO program (03/11/08 to 05/28/10)
Modified and tested my MRO ULDL Board design.
Advanced Sterling Engine Controller Project (ASRG) (11/1/06 to present)
Designed and tested an active power factor controller PWB and the FPGA using and Actel pro ASIC+ FPGA that controlled a sterling engine for use in NASA deep space probes. This des.
Worked the CEV proposal and DTO project (8/13/06 to 10/31/06)
Evaluated the spacewire bus and fire wire bus architectures for CEV and started the Illuminator controller design for DTO.
Mars reconnaissance Orbiter Project (MRO) (4/1/02 to 8/12/06)
Designed and tested a CCSDS compliant uplink and downlink (ULDL) CCA and the downlink fpga.
Advanced Special Programs (5/1/97 to 3/31/02)
Responsible for digital circuit design Actel Act II & III and Xilinx 4000E series FPGA's for high speed digital and dsp design, also and high speed digital data network(Switch Fabric Matrix) (Myrinet) designs.
Special Programs (5/96 to 5/1/97)
Responsible for convolutional encoder board and fpga design.
Descent Imaging Spectral Radiometer Project (DISR) (8/-91 to 5/96)
Responsible for microprocessor/digital circuit design for the instrument. Designed the computer that controlled the camera that took the pictures of Saturn's moon Titan during the descent. Used an advanced 1750A microprocessor and Actel FPGA's for the digital design. DISR is an instrument on the Huygens probe, which is part of the Cassini mission to Saturn.
Internal Research and Development, (4/91 to 8/91)
Responsible for evaluation of common microprocessor for several NASA space science instrument designs. Performed a preliminary design of an R3001 and a 1750A design and evaluated which one will best meet requirements.
Digital Microprocessor Designer, Gamma Ray Spectrometer Project (GRS) (10/86 to 4/91)
Responsible for the design, test and worst case analysis of three interconnected 80C86 circuits that collected and transmitted data from the GRS Instrument to the Mars Observer Spacecraft
Digital Microprocessor Designer, Orbital Spacecraft Consumables Resupply System Project (OSCRS) (7/86 to 10/86)
OSCRS was a study contract for a refueling system for the space shuttle. Responsible for applying the dual fault tolerant, majority voting system, based on my TOS design.
Product Integrity Engineer (PIE), Majority Vote Sequencer (MVS) for the Transfer Orbit Stage Project (TOS) (2/84 to 7/86)
Responsible for the design test of a dual fault tolerant 2 out of 3 majority voting system for sequencing the launch of the TOS. Awarded a Patent, #4,799,140. It is the first spacecraft to be entirely controlled autonomously by a microprocessor.
Product Integrity Engineer (PIE), Peacekeeper Missile Project, Launch Support System (LSS) (7/81 to 1/84)
PIE for the LSS Timing System and Test Operations switching unit. Responsible for the design and test of the countdown time/ hold time systems, and test control center switching unit, for the peacekeeper missile launch complex. In addition, I didSoftware/Hardware integration of test tool for LSS ground support equipment. Used a standard bus computer, designed the interface cards to LSS ground support equipment. Wrote the software (Pascal and Z80 Assembly language) for the system.
Engineer, High Density Digital Tape Recorders (HDDR) (1/80 to 7/81)
An HDDR is a high speed-high density tape recorder used for recording data from orbiting satellites. Worked part time (50%) doing circuit design and testing of new HDDR systems. Also worked part time (50%) doing new business proposals and systems design.
1973 toUNITED STATES AIR FORCE
1979Wing Command Post Training Officer (8/77 to 10/79)
Wing Command Post Operations Controller (4/77 to 10/79)
Weapons Systems Officer, Electronic warfare Officer F4E Fighter-Bomber (8/75 to 4/78)
OTHER
EXPERIENCE:8/72-10/73. Teacher, high school electronics and physics.
EmploymentFlexible on area of assigned work, but most interested in Circuit boad followed by FPGA design.
Objective: