Electrical Engineering Department
M.S. Final Oral Defense
STANDARD CELL LIBRARY FOR A-SI:H TFT DIGITAL CIRCUITS ON FLEXIBLE SUBSTRATES
by
Shrinivas Gopalan Uppili
September 11, 2008.
11:30.am
GWC 409
Committee:
Dr. David R. Allee (chair)
Dr. Lawrence T. Clark
Dr. Sameer M. Venugopal
Abstract
Hydrogenated amorphous silicon (a-Si:H) Thin Film Transistors (TFT) are traditionally used as backplane arrays for active matrix displays and occasionally as row or column drive electronics with current efforts focusing on flexible displays and drivers. This thesis extends flexible electronics to complex digital circuitry by designing a standard cell library for a-Si:H TFTs. The standard cell library developed enables layout automation with standard cell place and route tool, allowing the designer to work at the gate level abstraction. The goal is to develop a design flow for building a larger fully flexible digital system incorporating a display, sensor and microcontroller.
In this thesis the design and characterization of a novel standard cell library using n-channel a-Si: H TFT for flexible substrates like stainless steel and Polyethylene Naphthalate (PEN) are discussed. Since only n-channel transistors are available the gates are designed with a boot-strap pull-up network to ensure good output voltage swings. The library developed consists of 7 gates – 5 combinational (inverter, two input NAND (NAND2),two input NOR(NOR2), three input NOR(NOR3), two input multiplexor (MUX2)) and 2 sequential (latch and D type flip-flop). Test structures were also fabricated to obtain experimental delay vs. fanout data for the basic gates, namely inverter, NAND2 and NOR2. It was found that the gates fit to a linear delay vs. fanout model. Verification processes like extraction of electrical interconnection from layout, layout versus schematic (LVS) and standard cell place and route (SPR or APR) for layout automation are incorporated to the existing Tanner tool suite for bottom gate a-Si:H TFTs. A 3bit counter demonstrates the design of a simple finite state machine using the standard cells developed and hardware results are provided.
Lifetime testing results of a flip-flop are provided towards the end of the thesis document. Testing results reiterate the fact that boot-strap circuits provide extended operational lifetimes. The testing results helped correlate the simulation of threshold voltage shift models with both short term and long term aging. Further, the operating frequency of sequential circuits is constrained by the operational lifetime required in addition to combinational circuit delays and sequencing overhead of the flip-flop.