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Chip Designer

April16, 2007

SoC Design

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Please see below for address change or subscribe/unsubscribe instructions.

In this Issue:

1. Viewpoint: TK from Dave Weins (Suzanne Graham) for Mentor Graphics

***I have a backup viewpoint from Neutronix is this falls through***

2. Moore's Law Goes 3D

3. New Modeling Technology for Virtual Software Development

4. VSIA QIP Metric Available with Hard IP Extension

5. Parallel Fast Spice

6. Swedish Firm Introduces High-Capacity FPGA

7. Embedded Chip Enhances Automotive Dashboard Displays

8. In-Depth Coverage Links

> Semiconductor Industry Faces Structural Changes Around IP

> Third-Party IP—Curse or Blessing to SoC Development?

9. Featured Book

> Intelligent Sensor Design Using the Microchip dsPIC

10. Happenings -- Conferences

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1. Viewpoint - Exclusive

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Title TK

Dave Weins, Title, Mentor Graphics

(

Text TK.

Dave Weins is the Title at Mentor Graphics.

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2. News

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Moore's Law Goes 3D

IBM has revealed a new chip-stacking technology that could extend Moore's Law beyond its expected limits. The technology, called "through-silicon vias," lets different chip components be packaged much closer together andenables the move from horizontal 2D chip layouts to 3D chip stacking, which takes chips and memory devices that traditionally sit side by side on a silicon wafer and stacks them together on top of one another. The resultant compact stack reduces the size of the overall chip package and increases the speed at which data flows among the functions on the chip. The method relies on through-silicon vias—vertical connections etched through the silicon wafer and filled with metal. The first application of through-silicon via technology will be in wireless communications chips that power amplifiers for wireless LAN and cellular applications.

IBM

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3. News

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New Modeling Technology for Virtual Software Development

VirtutechInc.has announced Simics VMP, a performance-enhancing modeling technology that leverages hardware virtualization capabilities in Intel and AMD chips. Simics VMP gives developers near-native performance along with the benefits of virtualized software development, including integration with software debugging tools, deterministic execution, observability and controllability of the target hardware, and reverse execution. The technology, traditionally used to let multiple operating systems run on the same PC, maximizes performance and scalability while providing a user-friendly development environment. The virtual software development solution also letsdesignersuse hardware virtualization for arbitrary target hardware based on x86 processors. Simics VMP will be included in Virtutech's Simics platform in the second half of 2007.

Virtutech Inc.

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4. News

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VSIA QIP Metric Available with Hard IP Extension

The VSI Alliance (VSIA) has announce that the Quality IP (QIP) Metric version 3.0, which includes the hard IP extension, is now publicly available. In addition, the verification IP extension to the QIP Metric is entering beta testing. QIP version 3.0 includes enhanced support for hard IP quality metrics, including support for different types of hard IP as well as hierarchical evaluation and graphical results representations. Included in this release is the verification IP extension that includes QIP metrics for drivers and responders, monitors, bus functional models, and stimuli generators. The verification IP extension is will be released in a mid-2007 following the beta testing period.

VSI Alliance

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5. News

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Parallel Fast Spice

Magma Design Automation has announced the availability of the FineSim Pro Parallel Manager, which it claims to have the first parallel fast Spice capability. The product is based on Magma's native parallel technology and is designed for the verification of large, mixed-signal SoCs. The FineSim Pro Parallel Manager augments Magma's transistor-level circuit simulator,FineSim Pro. FineSim Pro includes three modes: Spice, fast Spice, and "hyper" Spice. FineSim Spice can be parallelized over multiple processors for linear speedup and higher capacity and all three modes can now be parallelized. FineSim Pro Parallel Manager can run the simulator over distributed networks or multiple-CPU workstations.

Magma Design Automation

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AberdeenGroup Benchmarking Survey

Hit Your Product Reliability Targets by More Than 96%

According to Aberdeen research, electronics companies -- facing pressure to reduce time to market while maintaining product reliability and product performance -- are struggling with challenges such an expert skills shortage and increasing verification time. Yet companies that are best in class at electronic design hit their engineering design deadlines 85% or more of the time and average 23% fewer re-spins than average companies. This leads to faster time to market, lower cost, and an advantage over the competition.

According to Electronics -- Correct by Design:

* Best in Class organizations are 50% more likely than average companies

to use design for manufacturability (DFM) tools in all phases of development.

* Best in Class firms are almost 40% more likely to be using advanced

verification software than other companies.

* Best in Class performers are three times more likely than laggards to

integrate design processes across departments.

Discover how your company can become Best in Class.

This $399 report is free for a limited time.

DOWNLOAD YOUR COMPLIMENTARY COPY

Unauthorized use or reproduction is forbidden.

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Take VDC's Survey on Embedded System Engineering Trends:

Get a free summary of the research findings and enter to win a $100 Amazon.com gift certificate

If you're a developer of embedded systems, processors, hardware, and/or software VDC wants to know about your experiences. VDC, an independent technology research firm, is conducting research on ESL (Electronic SystemLevel) design. The survey covers embedded hardware, system, and software engineering and VDC is looking for feedback from developers with recent experience in any of these areas. No experience with ESL design is required.

In appreciation of your participation, VDC will provide all respondents who complete the survey:

* A summary of the survey findings, and

* A chance to win one of three $100 Amazon.com gift certificates

(drawing to be held April 25th, 2007).

To participate in the survey and to learn more about ESL design, please visit:

+++++++++++++++++++++++++++++++++++++++++++++

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6. International News

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Swedish Firm Introduces High-Capacity FPGA

Hardi Electronics is releasing HAPS-50, its fourth-generation ASIC prototyping board. This new family of motherboards is based on the Xilinx Virtex-5 LX330. Several boards can be stacked or interconnected to handle any ASIC size up to and beyond 30 million gates. The first available board is the HAPS-52, with a capacity of 4 million ASIC gates. HAPS-52 has a number of new features, including more I/O and inter-FPGA connections, a global bus, more I/O-voltage regions, and a more flexible clocking scheme. The boards provide improved monitoring and self-test as well as remote configuration and setup. The HAPS-50 motherboards are compatible with previous generations and meet the HapsTrak standard.

Hardi Electronics AB

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7. International News

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Embedded Chip Enhances Automotive Dashboard Displays

Singapore's Fujitsu Microelectronics Asia has announced a system LSI chip that incorporates functions required for next-generation automotive devices into one chip. The new chip provides 2D and 3D graphics, an automotive communication control system, a program-protect function, and variety of media interfaces. It lets data mapping and information from car's navigation device or digital dashboard be integrated into the in-vehicle LAN. The new chip uses Fujitsu’s 90nm process technology and has a variegated peripheral I/O with features such as an ARM9 core anda graphics display controller. The chip uses USB as its multimedia system interface, CAN as its in-vehicle network controller, and IDE66 (parallel-ATA/ATAPI-4) as its hard-disk interface.

FujitsuMicroelectronics Asia

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8. In-Depth Coverage Links

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SoC designers can now take advantage of IP from other semiconductor companies to help deal with rising complexity and gate counts.To learn more, read Trent Poltronetti's "Semiconductor Industry Faces Structural Changes Around IP."

Chip Design Editorial Feature >

For successful SoC development, it is imperative that we begin to think of third-party IP in a new light. Not only must we redefine "quality" IP, but we must also open our thinking to the development and adoption of a fully integrated IP sub-system.To learn more, read Bill Martin's "Third-Party IP—Curse or Blessing to SoC Development?"

iDesign Editorial Feature >

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9. Featured Book

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Intelligent Sensor Design Using the Microchip dsPIC

By Creed Huddleston

ISBN: 0750677554

Publisher: Newnes (Elsevier Science and Technology Books)

Intelligent sensors can measure parameters efficiently and precisely as well as enhance and interrupt those measurements, transforming raw data into useful information. Huddleston's book gives readers an understanding of the issues involved when interfacing to specific types of sensors and offers insight into the real-world problems designers face using intelligent sensors. Software examples are implemented in both C and assembly language, and the source code is included on the accompanying CD. The examples provide a complete, easily extensible code framework for sensor-based applications as well as basic support routines. The book gives designers in-depth knowledge about a new microcontroller that offers some of the functionality of a DSP chip.

Newnes

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10. Happenings -- Conferences

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World Wireless Conference

Stanford Park Hotel, Stanford, CA

May 21-27, 2007

IEEE RFIC Symposium

Hawaii Convention Center, Honolulu, HI

June 3-5, 2007

International Interconnect Technology Conference

June 4-6, 2007

Hyatt Regency, Burlingame, CA

Design Automation Conference

San Diego Convention Center, San Diego, CA

June 4-8, 2007

CSS 2006

July 2-4, 2007

Banff, Alberta, Canada

Semicon West

Moscone Center, San Francisco, CA

July 16-20, 2007

wps2a.semi.org/wps/portal

Flash Memory Summit

Santa Clara Marriott, Santa Clara, CA

August 7-9, 2007

IEEE Custom Integrated Circuits Conference

Doubletree Hotel, San Jose, CA

September 16-19, 2007

Intel Developer Forum

Moscone Center West, San Francisco, CA

September 18-20, 2007

IEEE International SoC Conference

Ambassador Hotel, Hsinchu,Taiwan

September 26-29, 2007

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