Course Modification Proposal – Page 1/5

COURSE MODIFICATION PROPOSAL

College: [ CECS ] / Department: [ ECE ]

1.  Current Catalog Entry Information:

Subject Abbreviation and Number: [ ECE 527]

Course Title: [Application Specific Integrated Circuit Development]

Units: [ 3 ] units

General Education Section [ ] (if applicable)

2.  Date of Proposed Implementation: (Semester/Year): [ Fall ] / [ 2011 ] Comments

3.  Course Level:

[]Undergraduate Only / []Graduate Only / [X]Graduate/Undergraduate

4.  Nature of Request:

[] Delete Course (Note: Record of course will remain in inactive course file)

[] Change unit value from [ ] units to [ ] units

[] Change course type (classification) such as lecture-discussion, laboratory, activity, etc.:

From: [ ] units @ [] [] to [ ] units @ [] []

From: [ ] units @ [] [] to [ ] units @ [] []

[] Change course title to: []

[] Change course abbreviation “Short title” (Maximum of 17 characters and spaces) to

NEW Short Title: [ •••••••••••••••• ]

[X] Change current catalog course description (Attach current and proposed catalog course description)

Notes: If grading is NC/CR only, please state in course description. If a course numbered less than 500 is available for graduate credit, please state “Available for graduate credit in the catalog description.”

[] Change subject abbreviation number to: (Example: HSCI 100 to PT 105) [ ]

[] Change requisites (Prerequisites, Corequisites, Preparatory, Recommended Corequisites)

From:

To:

[] Change Current Basis of Grading

From: / []Credit/No Credit Only / []Letter Grade Only / []CR/NC or Letter Grade
To: / []Credit/No Credit Only / []Letter Grade Only / []CR/NC or Letter Grade

[] Add course to GE Section [ ]

[] Remove course from GE Section [ ]

[] Change course from GE section [ ] to GE section [ ]

[] Change course to a Community Service Learning course (CS)

[] Allow multiple enrollments within a semester.

[] Change number of times this course may be taken:

May be taken for credit for a total of [ ] times, or for a maximum of [ ] units

[] Multiple enrollments are allowed within a semester

[] Crosslist this course with [ ]

[] Other: [ ]

5.  Justification and Clarification of Request. (attach)

6.  Estimated Impact on Resources within the Department, for other Departments and the University. (None)

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(See Resource List)

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7.  Impact on other Departments’ programs. (None)

8.  Indicate which of the Program’s Measurable Student Learning Outcomes are addressed in this course. (No Change)

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(see Course Alignment Matrix and the Course Objectives Chart)

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9.  If this is a General Education course, indicate how the General Education Measurable Student Learning Outcomes (from the appropriate section) are addressed in this course. (N/A)

10.  Methods of Assessment for Measurable Student Learning Outcomes (No Change)

A.  Assessment tools

B.  Describe the procedure dept/program will use to ensure the faculty teaching the course will be involved in the assessment process (refer to the university’s policy on assessment.)

11.  Record of Consultation: (Normally all consultation should be with a department chair or program coordinator.) If more space is needed attach statement and supporting memoranda.

Date: / Dept/College: / Department Chair/Program Coordinator / Concur
(Y/N)
[ 3/9/10] / [ ECE ] / [ Dept. Vote: Ali Amini ] / [ YNIP ]
[3/17/10] / [ ME ] / [ Hamid Johari ] / [ YNIP ]
[3/17/10] / [ CS ] / [ Steven Stepanek ] / [ YNIP ]
[3/17/10] / [ MSEM ] / [ Behzad Bavarian ] / [ YNIP ]
[3/10/10] / [ CEAM ] / [ Steve Gadomski ] / [ YNIP ]
[ ] / [ ] / [ ] / [ YNIP ]

Consultation with the Oviatt Library is recommended for course modifications to ensure the availability of appropriate resources to support proposed course curriculum.

Collection Development Coordinator, Mary Woodley / Date
Please send an email to: / [3/9/10]

12.  Approvals:

Department Chair/Program Coordinator: / Date: / [ ]
College (Dean or Associate Dean): / Date: / [ ]
Educational Policies Committee: / Date: / [ ]
Graduate Studies Committee: / Date: / [ ]
Provost: / Date: / [ ]

Begin free format section below

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ATTACHMENT

Current catalog course description Begin free format section below

ECE 527 Application Specific Integrated Circuit Development (3)

Prerequisites: ECE 526/L. Corequisite: ECE 527L. A course covering concepts, techniques and methodologies used in modern VLSI design automation. The course builds on the foundation of hardware description languages and simulation taught in ECE 526 and proceeds to logic synthesis, static timing analysis, formal verification, test generation/fault simulation, and physical design, including floor planning, placement, routing, and design rule checking.

Proposed catalog course description Begin free format section below

ECE 527 Application Specific Integrated Circuit Development (3)

Prerequisites: ECE 526/L. Corequisite: ECE 527L. Study of the tools and

techniques used to develop application specific integrated circuits, including

mask programmed devices and field programmable circuits. Topics include

synthesis methodologies, performance tradeoffs and constraints. Asynchronous

interfacing is covered in detail for both single bit and bus interfaces. A non-

theoretical introduction to test and testability is also included.

Justification for request: To more accurately and more attractively describe what is really taught in the course.

Course Syllabus

ECE 527 – Application Specific Integrated Circuit Development

Department: Electrical and Computer Engineering

Course Number: ECE 527

Course Title: Application Specific Integrated Circuit Development

Credit Units: 3.0

Course Description

Study of the tools and techniques used to develop application specific integrated circuits, including mask programmed devices and field programmable circuits. Topics include synthesis methodologies, performance tradeoffs and constraints. Asynchronous interfacing is covered in detail for both single bit and bus interfaces. A non-theoretical introduction to test and testability is also included.

Prerequisites

ECE 526. Students need a thorough understanding Verilog for digital integrated circuit description.

Text

None

Software

Cadence NC Verilog simulator, Synopsys Design Compiler, Synopsys PrimeTime Static Timing Analyzer, Synopsys Test Compiler

Course Objectives:

After completing this course the students should be able to:

1. guard against metastability by properly synchronizing signals from different time domains

2. synthesize a netlist from a hierarchical set of Verilog circuit description files

3. modify a design for testability

4. create factory test vectors to ensure proper functioning of the fabricated circuits

5. perform static timing analysis on synthesized netlists

6. check for any design rule violations.

Topics Covered

1: Design issues. Clock crossings, metastability, synchronization, FIFOs. Clocks and resets.

2: Introduction to synthesis. Synthesis libraries, commands, constraints, scripts. Hierarchy and bottom-up methodology.

3: Test and testability.

4: Scan and BIST. Scan insertion using automated tools. Black boxes and IP cores.

5: Static timing analysis.

6: Physical design, place and route

7: Design rule checking.

8: Putting the final package together for release to the foundry.

Assessment Methods

Two mid-term examinations, one final examination and several homework assignments. Each consists of analytical and design problems.

Relationship Of Course To Program Outcomes

This course supports the achievement of the following outcomes:

a)  Ability to apply knowledge of advanced principles to the analysis of electrical and computer engineering problems.

b)  Ability to apply knowledge of advanced techniques to the design of electrical and computer engineering systems.

c)  Ability to apply the appropriate industry practices, emerging technologies, state-of-the-art design techniques, software tools, and research methods for solving electrical and computer engineering problems.

e)  Ability to communicate clearly and use the appropriate medium, including written, oral, and electronic methods.

h)  Ability to be competitive in the engineering job market and/ or be admitted to an excellent Ph.D. program.

Prepared by:

Ronald W. Mehler

Date: 4/30/10

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