FT/GN/68/00/21.04.15
SRI VENKATESWARA COLLEGE OF ENGINEERING
COURSE DELIVERY PLAN - THEORY Page 6 of 6
Department of Electronics and Communication Engineering / LP: VL7301Rev. No: 01
Date: 01.07.2015
M.E : EC Regulation: 2013
PG Specialization : APPLIED ELECTRONICS
Sub. Code / Sub. Name : VL7301 TESTING OF VLSI CIRCUITS
Unit : I
UNIT I TESTING AND FAULT MODELLING 9
Introduction to testing – Faults in Digital Circuits – Modeling of faults – Logical Fault Models – Fault detection – Fault Location – Fault dominance – Logic simulation – Types of simulation – Delay models – Gate Level Event – driven simulation.
Objective:
To know the various types of faults and also to study about fault detection and dominance.
SessionNo * / Topics to be covered / Ref / Teaching Aids
1. / Introduction to testing - Need for testing / 1-Ch-1 pg.9-10,
4-Ch-4 pg.57-60 / PPT
2. / Faults in Digital Circuits / 1-Ch-4 pg.93,
4-Ch-4 pg.60
2-Ch-2 pg.12-22 / PPT
3. / Faults Modeling - Logical fault models / 1-Ch-4 pg.93-95 / PPT
4. / Fault Equivalence, Fault Detection - Combinational and Sequential circuits / 1-Ch-4 pg. 95-106 / PPT
5. / Fault Location - Combinational and Sequential circuits / 1-Ch-4 pg. 106-108 / PPT
6. / Fault Dominance - Combinational and Sequential circuits / 1-Ch-4 pg. 109-110 / PPT
7. / Logic simulation - Types of simulation / 1-Ch-2 pg. 42-43 / PPT
8. / Delay models / 1-Ch-2 pg. 52-56
5-Ch-2 pg. 49 / PPT
9. / Gate level Event-driven simulation / 1-Ch-2 pg. 64-77,
4-Ch-5 pg. 101-103 / PPT
Content beyond syllabus covered (if any):
Fault Equivalence – Combinational and Sequential circuits
Course Outcome 1:
To apply test pattern for the detection of logical fault.
* Session duration: 50 minutes
Sub. Code / Sub. Name : VL7301 TESTING OF VLSI CIRCUITSUnit : II
UNIT II TEST GENERATION 9
Test generation for combinational logic circuits – Testable combinational logic circuit design – Test generation for sequential circuits – design of testable sequential circuits.
Objective:
To know the concepts of test generation for combinational and sequential circuits.
SessionNo * / Topics to be covered / Ref / Teaching Aids
10. / Test Generation for combinational logic circuits - One-dimensional Path sensitization and Boolean Difference / 2-Ch-4 pg.25-34 / PPT
11. / Test Generation for combinational logic circuits - D-Algorithm, Redundancy Identification (RID) / 3-Ch-4 pg.34-42,
4-Ch-7 pg.168-172 / PPT
12. / Test Generation for combinational logic circuits - PODEM / 2-Ch-4 pg.42-47
4-Ch-7 pg.186-192 / PPT
13. / Testable combinational logic circuit design - Reed-Muller Expansion Technique / 2-Ch-6 pg.199-202 / PPT
14. / Testable combinational logic circuit design - Three level OR-AND-OR design and Syndrome-testable design / 2-Ch-6 pg.202-210 / PPT
CAT I / PPT
15. / Test generation for sequential circuits - Iterative Combinational circuits / 2-Ch-4 pg.49-50 / PPT
16. / Test generation for sequential circuits - State Table verification / 2-Ch-4 pg.50-60 / PPT
17. / Design of testable sequential circuits / 2-Ch-6 pg.210-213 / PPT
18. / Design of testable sequential circuits - Scan-path technique / 2-Ch-6 pg.213-216
5-Ch-3 pg.108 / PPT
Content beyond syllabus covered (if any):
Redundancy Identification (RID)
Course Outcome 2:
To generate the test patterns for combinational and sequential circuit.
* Session duration: 50 minutes
Sub. Code / Sub. Name : VL7301 TESTING OF VLSI CIRCUITSUnit : III
UNIT III DESIGN FOR TESTABILITY 9
Design for Testability – Ad-hoc design – generic scan based design – classical scan based design – system level DFT approaches.
Objective:
To understand the concepts of test generation method - DFT.
SessionNo * / Topics to be covered / Ref / Teaching Aids
19. / Testability - Controllability and Observability / 1-Ch-9 pg. 343-346 / PPT
20. / Adhoc design for testability techniques - Test points, Initialization, Monostable Multivibrators / 1-Ch-9 pg. 347-353, 4-Ch-14 pg. 466 / PPT
21. / Adhoc design for testability techniques - Oscillator and clocks, Partitioning counters and shift registers / 1-Ch-9 pg. 353-355 / PPT
22. / Adhoc design for testability techniques - Partitioning of Large combinational circuits, Logical redundancy, Global feedback paths / 1-Ch-9 pg. 355-358 / PPT
23. / Generic scan based design - Full serial integrated scan / 1-Ch-9 pg. 364-366 / PPT
24. / Generic scan based design - Isolated serial scan and Nonserial scan / 1-Ch-9 pg. 366-368 / PPT
25. / Classical scan based design, Boundary Scan Design / 1-Ch-9 pg. 374 / PPT
26. / Classical scan based design - Level-Sensitive Scan Design (LSSD) / 1-Ch-9 pg. 374-381
2-Ch-6 pg. 216-219 / PPT
27. / System-level DFT approaches - system level busses, system-level scan paths / 1-Ch-9 pg. 382-383 / PPT
Content beyond syllabus covered (if any):
Boundary Scan Design
Course Outcome 3:
To explain the various techniques for testability.
* Session duration: 50 minutes
Sub. Code / Sub. Name : VL7301 TESTING OF VLSI CIRCUITSUnit : IV
UNIT IV SELF – TEST AND TEST ALGORITHMS 9
Built-In self-Test – test pattern generation for BIST – Circular BIST – BIST Architectures – Testable Memory Design – Test Algorithms – Test generation for Embedded RAMs.
Objective:
To study the concepts of test generation method - BIST.
SessionNo * / Topics to be covered / Ref / Teaching Aids
28. / Introduction to BIST concepts / 1-Ch-11 pg. 457-460, 6 / PPT/ICT
29. / Test pattern generation for BIST - Exhaustive testing, Pseudorandom testing, Pseudo-exhaustive testing / 1-Ch-11 pg. 460-462 / PPT
CAT II
30. / Test pattern generation for BIST - Logical segmentation, Constant-weight patterns, Identification of test signal inputs, Physical segmentation / 1-Ch-11 pg. 462-477 / PPT
31. / Circular BIST, Scan-Based Logic BIST / 1-Ch-11 pg. 495-500, 5-Ch-3 pg. 168-173 / PPT
32. / BIST Architecture - CSBL, BEST, RTS, LOCST, STUMPS / 1-Ch-11 pg. 483-489, 5 / PPT
33. / BIST Architecture - CBIST, CEBS, RTD, SST, CATS, BILBO / 1-Ch-11 pg. 489-505, 4-Ch-15 pg. 519-521 / PPT
34. / Testable Memory Design / 4-Ch-9 pg. 284-300 / PPT
35. / Test Algorithms / 5-Ch-4 pg. 206 / PPT
36. / Test generation for Embedded RAMs / 4-Ch-15 pg. 530-540 / PPT
Content beyond syllabus covered (if any):
Scan-Based Logic BIST
Course Outcome 4:
To understand the various BIST architecture and test algorithms.
* Session duration: 50 minutes
Sub. Code / Sub. Name : VL7301 TESTING OF VLSI CIRCUITSUnit : V
UNIT V FAULT DIAGNOSIS 9
Logical Level Diagnosis – Diagnosis by UUT reduction – Fault Diagnosis for Combinational Circuits – Self-checking design – System Level Diagnosis.
Objective:
To understand the fault diagnosis method.
SessionNo * / Topics to be covered / Ref / Teaching Aids
37. / Logical level diagnosis - basic concepts / 1-Ch-12 pg. 541-543 / PPT
38. / Diagnosis by UUT reduction / 1-Ch-12 pg. 554-555 / PPT
39. / Fault Diagnosis for Combinational Circuits / 1-Ch-12 pg. 556-557 / PPT
40. / Self-Checking design - multiple bit errors, Checking circuits and self-checking / 1-Ch-13 pg. 577-579 / PPT
41. / Self-Checking design - self-checking checkers, Parity-check function / 1-Ch-13 pg. 579-581 / PPT
42. / Self-Checking design - Totally self-checking m/n code and equality checkers, Berger code checker / 1-Ch-13 pg. 581-585 / PPT
43. / Self-Checking Combinational circuits / 1-Ch-13 pg. 585-587 / PPT
44. / Self-Checking sequential circuits / 1-Ch-13 pg. 587-589 / PPT
45. / System level Diagnosis / 1-Ch-15 pg. 633-643 / PPT
CAT III
Content beyond syllabus covered (if any):
NIL
Course Outcome 5:
To design a self-checking for combinational and sequential circuit.
* Session duration: 50 minutes
Sub. Code / Sub. Name : VL7301 TESTING OF VLSI CIRCUITSREFERENCES:
- M.Abramovici, M.A.Breuer and A.D. Friedman, “Digital systems and Testable Design”, Jaico Publishing House, 2002.
- P.K. Lala, “Fault Tolerant and Fault Testable Hardware Design”, Academic Press, 2012.
- P.K. Lala, “Digital Circuit Testing and Testability”, Academic Press, 2002.
- M.L.Bushnell and V.D.Agrawal, “Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits”, Kluwer Academic Publishers, 2002.
- A.L.Crouch, “Design Test for Digital IC’s and Embedded Core Systems”, Prentice Hall International, 2002.
- http://nptel.ac.in/courses/106103016/30
Prepared by / Approved by
Signature /
Name /
R.KOUSALYA
/ Dr.S.GANESH VAIDYANATHANDesignation /
Assistant Professor
/ HoD-ECDate / 01.07.2015 / 01.07.2015
Remarks *:
Remarks *:
* If the same lesson plan is followed in the subsequent semester/year it should be mentioned and signed by the Faculty and the HOD