Digital Electronics (EO128)
s
School of Environment and Technology
Division of Engineering and Product Design
Semester-Two Examinations,May-June2010
B.ENG. HONOURS DEGREE COURSE
DIGITALELECTRONICS (EO128)
EXAMINERS: Mr. C.S. Knight & Dr. S.C. Busbridge
Instructions to Candidates:
The time allowed isTWO hours
Answer ALLFIVE questions
The total number of questions is FIVE
Each question carries20 marks
This is a CLOSED-BOOK examination
Special Requirements:
Data-sheet for the 74F00 integrated circuit (first three pages only)
Question 1
(a)Explain briefly what is meant by the terms ‘combinational logic’ and ‘truth table’.
(4 marks)
(b)Draw a circuit diagram to directly implement the logical expression.
Using Boolean algebra, show how this expression could be simplified to.
(8 marks)
(c)Write down the truth table for the logical expression in part (b)and show how it could be implemented using a 3-to-8 line multiplexer.
(8 marks)
Question 2
(a)Explain briefly the difference between the terms “synchronous” and “asynchronous” as applied to sequential logic systems.
(4 marks)
(b)Write down the truth table and the excitation table for a J-K flip flop. Hence show how D-type and T-type flip flops may be derived from the operation of a JK flip flop.
(4 marks)
(c)Design a single digit asynchronous Binary Coded Decimal (BCD) up counter, giving your answer in the form of a circuit diagram. State an important potential problem that is likely to arise with this type of circuit design, particularly as the complexity increases.
(6 marks)
(d)A synchronous state machine is required to produce the following output sequence: 00, 10, 11, 01... (the sequence then repeats). Produce a state table for this design using D-type flip flops, and use Karnaugh maps to derive logic inputs for the flip-flop inputs (note that the circuit diagram is NOT required).
(6 marks)
Question 3
Part of a digital system contains a 74F00 integrated circuit (IC). The power supply to this system varies from 5.0V down to 4.5V.
A data sheet for the 74F00 device is supplied as a separate document.
(a)For this IC, determine the following:
(i)The minimum voltage for a logic '1' output.
(1 mark)
(ii)The worst-case noise margin.
(3 marks)
(iii)The maximum output sink current for a logic ‘0’ output.
(1 mark)
(iv)The maximum propagation delay.
(1 mark)
(b)The input of one of the gates is to be connected to a simple single-pole-single-throw (SPST) switch.
Design a suitable circuit such that when the switch is closed, a logic ‘1’ is applied to the 74F00 input. Show all your calculations.
(7marks)
(c)Explain what is meant by the term ‘tristate’ with respect to a digital output. Draw the circuit symbol for a tristate inverting buffer and explain its function.
Under what circumstances might this type of device be used?
(7marks)
Question 4
A waveform generator is to be designed using falling-edge-triggered T-type flip-flops with appropriate additional combinational logic for the feedback circuitry. The required waveform is given below in Figure Q4.
Figure Q4
(a)Draw up a full state diagram for this function.
(6 marks)
(b)Hence produce a state table and derive minimisedequations for the flip-flop inputs. Note that a circuit diagram is NOT required.
(14 marks)
Question 5
Study carefully the Multisim synchronous ring-counter circuit below (Figure Q5).
Figure Q5
(a)Give a brief description of the operation of the circuit including the function of the clock, preset and clear inputs. In what mode are the JK flip-flops operating?
(5 marks)
(b)Derive the full state diagrams for the circuit. Show clearly how you obtained these.
(7 marks)
(c)Hence draw waveforms for the main sequence showing the clock and all three outputs.
(6 marks)
(d)Why is a ‘preset’ input absolutely necessary for this circuit?
(2 marks)
Page 1 of 5