Xilinx ISE Design Suite 10.1

Product Backgrounder

Embargoed News: March 24, 2008

Enhanced Productivity and Performance for Complex Design

Today, FPGA design is as sophisticated as any fixed-architecture implementation alternative, with gate counts and manufacturing processes pushing the leading edge. No longer are FPGAs considered only a scaled-back prototyping platform; today’s multi-million-gate devices implemented in processes as advanced as 45-nanaometer (nm) and offered at competitive price-points are fully capable of powering high-performance, high-volume products. Combined with their traditional benefits of extreme flexibility and programmability, as well ease-of-design, FPGAs are, in many cases, the best option for a wide variety of demanding, cost-sensitive and dynamic applications in computer, communications, consumer and automotive markets. So it is imperative that FPGA design tool environments keep pace with the device capabilities for which they are targeted.

As FPGA design complexity continues to increase and advanced manufacturing processes introduce new implementation challenges, designers must be armed with solutions that simultaneously deliver improved tool performance, efficiency and functionality. Chief among their concerns are design tool throughput (i.e. fast run times); ease-of-use and productivity in order to reach timing closure and perform design spins quickly; and advanced capabilities to address issues such as timing and low power.

At the same time, design disciplines are converging and design teams need integrated solutions for all their implementation choices. A single control point for designing logic, embedded and DSP applications enhances productivity and facilitates true system design with a system-on-chip (SoC) FPGA.

With the latest release of its award-winning and widely-popular ISE® tool suite, Xilinx once again sets the standard for design solution capabilities, tracking to the advancements it has made in its latest high-performance Virtex®-5 and low-cost Spartan®-3 FPGAs. With ISE Design Suite 10.1, Xilinx addresses head-on the most demanding challenges faced by designers of advanced FPGAs, and for the first time offers a single solution that unites the needs of logic, embedded and DSP designers.

Building on a legacy of leadership –ISE has consistently been named the industry’s best in independent user surveys over the past several years – Xilinx now offers an enhanced, full-featured, front-to-back design environment that delivers performance, productivity and critical features for complex FPGA design. ISE Design Suite 10.1 delivers intuitive and productivity-enhancing tools for each step in the design process, from system-level design exploration, to software development and HDL-based hardware design, through to verification, debug and integration with PCB design.

Speed is King

Engineers have an insatiable desire for faster performance, especially as designs get larger and more complex. The ISE Design Suite 10.1 delivers significantly faster implementations with an average of 2X faster run-times, allowing designers to complete more turns per day. The enhanced design environment now offers SmartXplorer technology, developed specifically to address the top challenges of the design community – timing closure and productivity. SmartXplorer technology leverages distributed processing across multiple Linux machines to enable even more implementation runs per day, and up to 38 percent faster performance by exploiting the advantages of distributed processing and multiple implementation strategies. SmartXplorer technology also provides tools that allow users to monitor each run with individual timing reports.

Ultimate Productivity with PlanAhead Lite & Strategy Based Implementation

Designers don’t just want their tools to run faster; they need more efficient methodologies and features to achieve significant improvements in productivity.

ISE Design Suite 10.1 can be configured with the robust features of its award-winning PlanAhead™ design analysis tool that delivers floorplanning and analysis capabilities that dramatically reduce design time. PlanAhead streamlines the design step between synthesis and place and route. Designers can visualize the critical path and floorplan to improve performance. The result is a significant reduction in both the number and the length of design iterations. This methodology allows designers to divide a larger design up into smaller, more manageable blocks and focus efforts toward optimization of each module, improving performance and quality of the entire design.

With the availability of the PlanAhead Lite tool in ISE 10.1 Foundation™, users have access to a subset of the powerful floorplanning and analysis capabilities of the full-featured PlanAhead design and analysis tool. Included at no additional cost, PlanAhead Lite features the revolutionary PinAhead technology, an intuitive solution designed to simplify the complexities of managing the interface between the target FPGA and PCB. PinAhead technology facilitates early and intelligent pinout definition to eliminate many of the pinout related changes that typically happen downstream by performing design rule checks during interactive pin placement. Once the pin assignments have been completed, PinAhead provides the ability to export I/O port information through either comma separated value (CSV) files or via VHDL or Verilog headers.

With ISE Design Suite 10.1, Xilinx simplifies the process of determining optimal implementation settings. Designers now have the ability to specify and set their own unique design goals, whether they are working to maximize performance, optimize device utilization, reduce dynamic power, or minimize implementation time. For example, by specifying “area reduction” as the primary goal, designers can realize an average of 10 percent better logic utilization.

Power Analysis and Optimization for the Deep Sub-Micron era

Industry studies show meeting power budgets is a growing challenge for FPGA designers, especially as process geometries continue to shrink. The ISE Design Suite 10.1 provides capabilities for users to analyze power requirements early in the design and optimize dynamic power throughout the design process.

The second generation XPower power analysis tool enhances power estimation by providing an improved user interface to make it easy to analyze power by blocks, hierarchy, power rails and resources used. Information is presented in both text and HTML report formats. This is a significant advance from the static estimation web pages offered by other logic providers and a leap forward in providing accurate power dissipation information.

ISE Design Suite 10.1 provides power optimization that’s both convenient and extensive. Using the integrated ‘power optimization design goal’ feature, users have a simple, one-step process to specify power optimization. With improvements in the map and place & route algorithms, users can reduce dynamic power in their designs by an average of 10 percent for 65nm Virtex-5 devices and an average of 12 percent with Spartan-3 generation FPGAs.

Simplifying System Design

Because today’s complex SoCs contain multiple sub-systems performing different functions, the design environment must be able to support a variety of implementation technologies in a cohesive way. ISE Design Suite 10.1 provides greater flexibility in design construction, enabling a wider use of embedded and DSP subsystems in designs. The new release - unified for logic, embedded and DSP - offers improved ease-of-use for implementing a combination of components. It includes unified interoperability, which allows users to easily add System Generator modules within the ISE Project Navigator. Inter-tool integration enhancements between EDK and System Generator for DSP technologies enable more sophisticated FPGA SoC design incorporating both embedded and signal processing.

ISE Design Suite 10.1 Configurations

Xilinx ISE Design Suite 10.1 software release provides a customizable environment that can be tailored to suit a designer’s specific needs:

ISE Foundation is the industry’s most complete programmable logic design environment. ISE Foundation supports all Xilinx leading CPLD and FPGA product families and provides everything needed to complete any logic design, running standalone or tightly integrated with third-party EDA design tools. ISE Foundation includes ISE Simulator Lite at no additional charge, with an available upgrade to ISE Simulator full version. ISE Foundation is available for Microsoft Windows and Linux.

ISE WebPACK is available for download from the Web at no charge. ISE WebPACK™ provides everything needed to complete programmable logic designs targeting Xilinx CPLDs and low-density FPGAs, and contains the same tools found in industry-leading ISE Foundation. ISE WebPACK is available for Microsoft Windows Linux.

System Generator for DSP – The System Generator for DSP suite provides a complete environment for designing high-performance DSP systems with Xilinx FPGAs. High-level abstractions can be automatically compiled into highly parallel systems with no loss in performance through seamless integration of system modeling and automatic code generation from Simulink and MATLAB (The MathWorks, Inc.). The System Generator software is an integral component of the Xilinx XtremeDSP solution which delivers state-of-the-art silicon, design tools, intellectual property cores, development kits and specialized design and educational services.

AccelDSP Synthesis Tool - The AccelDSP™ Synthesis Tool automates the generation of synthesizable RTL models directly from floating-point MATLAB® M-files. With the AccelDSP Synthesis Tool, an algorithm written in the MATLAB language drives the entire design and verification flow. All major steps from floating-point definition to gate-level implementation are derived from this MATLAB source, and can be easily controlled through an intuitive user interface.

Xilinx Platform Studio (XPS) – The Platform Studio suite simplifies, abstracts, and accelerates the design of embedded subsystems with the PowerPCä hard processor core and Xilinx MicroBlazeä soft processor core targeting Xilinx FPGAs. The XPS suite is conveniently bundled with a processing IP library, software drivers, documentation, reference designs and the MicroBlaze soft processor IP core as part of the Xilinx Embedded Development Kit (EDK).

PlanAhead Design and Analysis Tool – The PlanAhead tool enables FPGA designers to achieve superior results by streamlining the step between synthesis and place-and-route — hierarchical floorplanning — commonly used by ASIC designers. This approach significantly reduces both the number and length of design iterations and produces an average of 15% additional improvement in design performance. PlanAhead users can quickly examine “what if” scenarios to identify and fix potential problems early, and also group critical paths and modules to increase routability through connectivity analysis and utilization control.

ChipScope Pro Debug and Verification – The ChipScope™ Pro analyzer enables on-chip, real-time verification and debug of FPGA designs while the device is interacting with the entire system, delivering 50 percent faster verification cycles versus traditional debug methods. The ChipScope Pro tools also work directly with Agilent logic analyzers for even deeper FPGA signal analysis.

ISE Simulator - ISE Simulator provides a complete, fully featured HDL simulator integrated within the ISE environment. ISE Simulator comes in two versions. ISE Simulator Lite is included at no charge with all ISE configurations, providing an ideal solution for CPLD and low-density FPGA designs that is limited to 10,000 lines of HDL source code. The full ISE Simulator version supports any design density and available as a low-cost add-on option to ISE Foundation.

ModelSim Xilinx Edition III – ModelSim XE III is a complete PC hardware description language (HDL) simulation and debug environment that enables designers to verify the HDL source code and functional and timing models of their designs. MXE III provides 100 percent VHDL and Verilog language coverage and includes a source code viewer/editor, waveform viewer, design structure browser, list window, and other features designed to enhance productivity.

ISE Design Suite 10.1 Product Backgrounder Page 5 March 2008